STM32 shadow register


Last article《Detailed explanation of STM32 basic timer》The shadow register is mentioned in. The shadow register will be described in detail below.

01. General

In the timer block diagram, there is a small detail. There is a shadow under some registers

Those with these shadows indicate that there are shadow registers in these registers.

There is also a description of the shadow register in the legend:

According to the control bit, after the U event, the contents of the preloaded register are transferred to the valid register. This is the description of the shadow register.

The shaded register (autoreloadregister) indicates that physically, this register corresponds to two registers. One is a register that the programmer can write or read, which is called preloadregister, and the other is a register that the programmer can’t see but really works in operation, which is called shadow register.

Here are three register names




My understanding here is that autoreloadregister auto reload register is a conceptual register. You can find the definition of each bit in the register table. It is composed of preloadregister and shadow register. What users can access, modify or read are preloaded registers. St only opens them (shadow registers are not open to users). In fact, they are arr registers.

The benefits of designing preloadregister and shadowregister are:

All shadow registers that really need to work can be updated to the content of the corresponding preloadregister at the same time (when an update event occurs), which can ensure that the operations of multiple channels can be synchronized accurately. If there is no shadowregister, or preloadregister and shadowregister are straight through, that is, when the software updates preloadregister, the shadowregister is updated at the same time, because the software cannot update multiple registers at the same time, resulting in the time sequence of multiple channels can not be synchronized. If other factors (such as interrupt) are added, The timing relationship of multiple channels may be unpredictable.

There are three types of shaded registers:



3、CCR(Capture/Comparex Register)



In the description of prescaler:

It is based on a 16-bit counter controlled through a 16-bit register(in the TIMx_PSC register).It can be changed on the fly as thiscontrol register is buffered. The new prescaler ratio is taken intoaccount at the next update event.

Excerpt from stm32f207 reference manual

Since the control register has a buffer function, the prescaler can be changed in real time. The new prescaler will be adopted when the next update event occurs.

Prescaler 1   Change to 2   Counter timing diagram at

Here, we can see that there is a shadow register in the prescaler register, but there is no control bit to control it. Its preload register and shadow register are connected.

The working mode is as follows:

be careful:

In the st manual, the shadow register is described as a buffer, and the shadow register of the prescaler is described as a register with a buffer function. among

It is also described here as timx_ The ARR register is not buffered.


Control bit:

The time base unit is described as follows

The content of the preload register are transferred into theshadowregister permanently or at each update event (UEV), depending on theauto-reloadpreload enable bit (ARPE) in TIMx_CR1 register.

Excerpt from stm32f207 reference manual

The contents of the preloaded register can be transferred either directly to the shadow register or to the shadow register every time an update event (UeV) occurs, depending on timx_ CR1   The auto reload preload enable bit (ARPE) in the register.

Timx_ The ARPE bit of CR1 determines the time sequence in which the preloaded register data is transferred into the shadow register.

Counter sequence diagram, ARPE = 0   Update event on (timx_arr)   Not preloaded).

As can be seen from the above two figures, if you count up and change the automatic overload register to 0x36 before reaching 0x36, an action will be generated when the count reaches 0x36.

Counter sequence diagram, ARPE = 1   Update event on (timx_arr)   Preload).

It can be seen from the above two figures that when counting up, the automatic reload preload register is modified to 0x36 before it reaches 0x36, there will be no action when counting to 0x36, and the automatic reload preload register value will be assigned to the automatic reload shadow register at this time.

There are two ways to transfer from the preload register arr to the shadow register, one is to update immediately, the other is to update after the trigger event; These two methods mainly depend on the “ARPE” bit in register timx – > CR1;

  1. ARPE = 0, when the ARR value is modified, the value of the shadow register is updated immediately;

  2. ARPE = 1, when the ARR value is modified, the value of the shadow register can be updated only after the next event UeV occurs;

How to change the value of the shadow register immediately instead of the next event; The method is as follows

1. ARPE = 0.

TIM_ARRPreloadConfig(ch1_Master_Tim,  DISABLE );

2. ARPE = 1.

TIM_ARRPreloadConfig(ch1_Master_Tim,  ENABLE);

After changing the preload register, we immediately set the UeV event, that is, change the UG bit of EGR register, as follows

TIM1->ARR   =    period-1;    // Set cycle

The working mode is as follows:

04、CCR(Capture/Comparex Register)

There are also text descriptions in the counter mode:

The UEV event can be disabled by software by setting the UDIS bit inthe TIMx_CR1 register. This is to avoid updating the shadow registerswhile writing new values in the preload registers。

Excerpt from stm32f207 reference manual

Timx through software_ Udis position 1 in the CR1 register inhibits the update event UeV event. This avoids updating the shadow register when a new value is written to the preload register.

Timx_ The udis bit in the CR1 register indirectly determines whether the pre installed register data is passed into the shadow register.

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