STM32 DAC details

Time:2021-11-20

The previous article introduced《Stm32adc details》, since there is an analog to digital ADC module, there must be a digital to analog DAC module. As the name suggests, this module only has the supplementary function of ADC. It converts digital binary values to analog voltage outputs. DAC module has many uses, including audio generation, waveform generation and so on. Generally, in most 8-bit microcontrollers, this module is not available, and its requirements can be slightly met by pulse width modulation (PWM). Part of the reason is that their hardware resources and running speed are relatively low. All STM32 microcontrollers have PWM module, but high-capacity STM32 also has DAC module. Stm32dac module is not very complex, and its working principle is similar to ADC module.

01. Introduction to DAC

According to the stm32f207 data book, stm32f207 has two DAC modules.

Each DAC has independent channels, and the corresponding gpios are PA4 and Pa5 respectively. For the reuse functions and additional functions of GPIO, click《Stm32adc details》There were detailed explanations.

In addition to the pins of DAC output, there are other related pins

Note: enable DAC   Channel x   After, the corresponding GPIO   Pin (PA4)   Or Pa5) will automatically connect to the analog converter output (dac_outx). In order to avoid parasitic current consumption, PA4 should be replaced first   Or Pa5   The pin is configured to analog mode (AIN).

The following simplified block diagram shows the main components of the stm32dac module.

02. DAC conversion

As can be seen from the block diagram, the DAC is directly controlled by the dorx register, but can not write data directly to the dorx register. Instead, it is indirectly transmitted to the dorx register through dhrx to realize the output control of the DAC.

Register DAC cannot be directly_ Dorx writes data. Any data output to DAC channel x must be written to DAC_ Dhrx register (data is actually written to dac_dhr8rx, dac_dhr12lx, dac_dhr12rx, dac_dhr8rd, dac_dhr12ld, or dac_dhr12rd register).

  1. If hardware trigger (tenx position 0 of register dac_cr1) is not selected, it is stored in register DAC_ The data of dhrx will be automatically transferred to the register DAC after one apb1 clock cycle_ DORx;

  2. If the hardware trigger (tenx position 1 of register dac_cr1) is selected, the data transmission is completed after 3 apb1 clock cycles after the trigger occurs.

Once the data is removed from the DAC_ Load dhrx register into DAC_ The output of dorx register is valid after the time tsettling. The length of this time will vary according to the power supply voltage and analog output load.

DAC control register (dac_cr)

Dmaen1: DAC channel 1dma enable (DAC Channel1 DMA enable). We do not use DMA, so it is set to 0

Mamp1 [3:0]: we do not use the DAC Channel1 mask / amplitude selector, so these bits are also set to 0

WAVE1 [1:0]: DAC Channel1 noise / triangle wave generationenable is not used, so it is also set to 0

Ten1: DAC Channel1 trigger enable. We don’t need to trigger, so it is set to 0

Tsel1 [2:0]: DAC Channel1 trigger selection note: this bit can only be set when ten1 = 1 (DAC Channel1 trigger enable). We set ten1 to 0, so we don’t need to set these bits. The default is 0

Boff1: turn off the DAC channel 1 output buffer (DAC Channel1 output buffer disable). We turn off the output buffer, so it is set to 1

En1: DAC Channel1 enable: we want to enable the DAC channel, so it is set to 1.

03. Function description

The DAC equivalent circuit of STM32 is as follows

The output buffer shown in this circuit operates on an internal 3.3V power supply. As with most operational amplifiers operating on a single power supply (rather than + / – dual power supplies), the output swing will never really achieve the goal. However, as shown in the circuit, there are two internal switches (S1 and S2) that can be controlled by registers. Turning them on will connect the “dacint” signal directly to the “dacout” pin through two resistors in series (RA and Rb). As a reference, RA + RB is about 15K.

According to the selected configuration mode, the data is written to the specified register as follows:

Single DAC channel x, 3 cases:

  1. 8-bit data right alignment: the user must write the data to the register DAC_ Dhr8rx [7:0] bit (actually stored in register dhrx [11:4] bit);

  2. Left alignment of 12 bit data: the user must write the data to the register DAC_ Dhr12lx [15:4] bit (actually stored in register dhrx [11:0] bit);

  3. Right alignment of 12 bit data: the user must write the data to the register DAC_ Dhr12rx [11:0] bit (actually stored in register dhrx [11:0] bit).

Generally, the third method is adopted: there are more right alignment of 12 bit data.

According to the DAC_ For the operation of dhryyx register, after corresponding shift, the written data is transferred to dhrx register (dhrx is the internal data storage register x). Subsequently, the contents of the dhrx register are either automatically transmitted to the dorx register, or transmitted to the dorx register by software trigger or external event trigger.

Dual DAC channels, there are three cases:

  1. 8-bit data right alignment: the user must write the DAC channel 1 data to the DAC register_ Dhr8rd [7:0] bit (actually stored in register dhr1 [11:4] bit) writes DAC channel 2 data to register DAC_ Dhr8rd [15:8] bit (actually stored in register dhr2 [11:4] bit);

  2. Left alignment of 12 bit data: the user must write the DAC channel 1 data to the DAC register_ Dhr12ld [15:4] bit (actually stored in register dhr1 [11:0] bit) writes DAC channel 2 data to register DAC_ Dhr12ld [31:20] bit (actually stored in dhr2 [11:0] bit of register);

  3. Right alignment of 12 bit data: the user must write the DAC channel 1 data to the DAC register_ Dhr12rd [11:0] bit (actually stored in register dhr1 [11:0] bit) writes DAC channel 2 data to register DAC_ Dhr12rd [27:16] bit (actually stored in register dhr2 [11:0] bit).

04. DAC output voltage

When the reference voltage bit of the DAC is VREF +, the digital input is linearly converted into an analog voltage output through the DAC, with a range of 0 to VREF +.

The output voltage on any DAC channel pin satisfies the following relationship:

DAC output = VREF x (DOR / 4095).

Note: at this time, the right alignment of 12 bit data should be selected.

05. Code configuration

DAC configuration

void DAC1_Config(void)
{
  DAC_InitTypeDef  DAC_InitStructure;
  GPIO_InitTypeDef GPIO_InitStructure;
  
  /* DMA1 clock and GPIOA clock enable (to be used with DAC) */
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
  
  /* DAC Periph clock enable */
  RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
  
  /* DAC channel 1 & 2 (DAC_OUT1 = PA.4)(DAC_OUT2 = PA.5) configuration */
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
  GPIO_Init(GPIOA, &GPIO_InitStructure);
  
   /* DAC channel2 Configuration */
  DAC_InitStructure.DAC_Trigger = DAC_Trigger_None;
  DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
  DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
  DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable;
  DAC_Init(DAC_Channel_1, &DAC_InitStructure);
 
  /* Enable DAC Channel2 */
  DAC_Cmd(DAC_Channel_1, ENABLE);
}

Set output voltage

//Set channel 1 output voltage

The test case is very simple, that is, repeatedly output 1.2V and 3.0V voltages

while (1)

Download verification

Hardware and software open source address:

https://github.com/strongercjd/STM32F207VCT6

Click to view the album where this article is located,Stm32f207 tutorial

Pay attention to the official account and receive the update at the first time.

Recommended Today

Single case mode can also play flowers

1、 Singleton mode 1. What is singleton mode (1) Singleton mode [singleton pattern:] definition: Ensure a class has only one instance, and provide a global point of access to it. Ensure that a class has only one instance and provide a global access point to it (only instance objects are allowed to be obtained through […]