Ruffian Heng embedded: measured the limit overturning frequency of ordinary GPIO and high-speed GPIO on i.mxrt1010

Time:2022-4-27

Hello, I’m ruffian Heng, a serious technical ruffian. What ruffian Heng introduced to you today isi. Normal GPIO and high-speed GPIO limit flip frequency on mxrt1010

Last articleTalk about the differences and usage between ordinary GPIO and high-speed GPIO on i.mxrt1xxx, ruffian Heng introduced the difference between ordinary GPIO and hsgpio in i.mxrt1xxx Series in principle. Today, let’s measure their limit turning frequency to see how different they actually behave. The test chip selected this time is i.mxrt1010. Functionally, this chip is the little brother of the current i.mxrt1xxx series, but don’t underestimate it, because it is the model launched later. The design team of NXP has made special performance optimization for it in some aspects, including hsgpio performance. If you don’t say much, start the test:

1、 Test preparation

1.1 test board and test point

The selected board is the official mimxrt1010-evk of NXP, and GPIO is connected to the LED light on the board_ 11. Looking through the chip reference manual, this pad can be equipped with either ordinary GPIO (gpio1 [11]) or hsgpio (gpio2 [11]). It is an ideal pad. We choose this pad for testing. In addition, the final I / O output waveform shape is also related to the peripheral drive circuit, so it is also necessary to explain clearly here:

  • Note: the oscilloscope model used is Tektronix mdo3024, with a bandwidth of 200MHz and a sampling rate of 2.5gs/s

1.2 I / O flip test code

We can test the project directly in \ SDK_ 2.11.0_ EVK-MIMXRT1010\boards\evkmimxrt1010\driver_ examples\gpio\led_ Modify the output routine. In order to try to show the ultimate performance of GPIO without being disturbed by other bottleneck factors, the project build with the highest code execution performance is selected here (that is, the code segment is in ITCM and the data segment is in dtcm).

I / O initialization code is very simple, inDifferences and usage between ordinary GPIO and high-speed GPIOIt’s all explained clearly in the article. There is only one note here. In order to unify the final I / O output effect, whether it is used for ordinary GPIO or hsgpio, We all directly configure the test pad to the fastest 200MHz operating frequency (the 50 / 100 / 150 / 200MHz operating frequency configuration supported by the pad is different, which mainly affects the signal amplitude response, but the four speed configurations measured by PI Ziheng have the same effect on the output of 100MHz I / O flip signal (only for the waveform angle observed at the oscilloscope end), and all we see are sine waves of standard amplitude):

void io_test_init(bool useNormalGpio)
{
    gpio_pin_config_t led_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
    CLOCK_EnableClock(kCLOCK_Iomuxc);      
    IOMUXC_SetPinMux(IOMUXC_GPIO_11_GPIOMUX_IO11, 0U); 
    // Fast Slew Rate, R0/7, 200MHz
    IOMUXC_SetPinConfig(IOMUXC_GPIO_11_GPIOMUX_IO11, 0x70F9U);
    if (useNormalGpio)
    {
        // GPIO1
        IOMUXC_GPR->GPR26 &= ~(1u << 11);
        GPIO_PinInit(GPIO1, 11, &led_config);
    }
    else
    {
        // GPIO2
        IOMUXC_GPR->GPR26 |= (1u << 11);
        GPIO_PinInit(GPIO2, 11, &led_config);
    }
}

In GPIO module, there are two registers related to level output control, one is Dr register and the other is Dr register_ Toggle registers can be used to flip the output level. There are three common level reversal methods shown in the following code. Under the condition of low reversal frequency, the three methods are equivalent, but under the condition of limit reversal frequency, the performance of the three methods is not completely consistent. The measured results in the next section will tell you:

void io_ test_ run(void)

1.3 chip system clock configuration

  Differences and usage between ordinary GPIO and high-speed GPIOAs mentioned in the article, the common GPIO clock source is IPG bus, while the hsgpio clock source is AHB bus. Therefore, the AHB / IPG clock configuration in the test project will affect the final I / O flip limit frequency. The following figure shows the hsgpio path in the i.mxrt1010 kernel structure, which is actually a little different from the hsgpio path in the i.mxrt1060/1170 kernel structure, which is also the optimization of i.mxrt1010.

led_ The default system clock configuration in the output routine. The AHB / core clock comes from pll6 – 500MHz, AHB_ Podf is set to 0 (i.e. no frequency division), while the clock source of IPG bus is fixed from AHB / core, and can only be divided by 1 / 2 / 3 / 4 based on it. We know that IPG bus only supports 150MHz at most, so in this case, IPG bus_ Podf can only be set to 3 (Quad frequency), and the IPG clock is actually 125MHz. Obviously, hsgpio access can obtain the optimal performance, but ordinary GPIO can not achieve the optimal performance.

PLL6, CCM_ ANALOG->PLL_ ENet [enet_500m_ref_en] = 1'b1, fixed 500MHz

In order to test the optimal performance of ordinary GPIO, we need to test a new system clock configuration at the same time. The clock source of AHB / core is pll2_ PFD3, configure this source to 452.6 MHz, AHB_ Podf is still set to 0, so IPG_ Set podf to 2 (three frequency division) to obtain 150.8mhz IPG clock. At this time, ordinary GPIO access can get the best performance, but hsgpio access will lose point performance.

PLL2,CCM_ ANALOG->PFD_ 528 [pfd3_frac] = 21, i.e. 528mhz * 18 / PFD3_ FRAC = 452.57MHz

2、 Test waveform results

The preparatory work has been completed. Now it is time for the oscilloscope to connect to the board and start the actual measurement. According to the combination, there are 12 results of clock configuration (x2) * I / O type (x2) * turnover method (x3). Only the waveform results obtained by three turnover methods of hsgpio at 500MHz AHB / core clock frequency are posted here. See the last section for all test results.

The first is the waveform result obtained by the exclusive or bit operation of GPIO – > Dr register. In order to reduce the impact of the execution of while (1) on the flip frequency (after all, this B.N jump instruction also consumes CPU cycles), we add ten flip codes in while (1), take 5 / 10 waveform cycles to average the statistical results, and finally get the flip frequency of 22.946 MHz, which seems to have an average effect. From the assembly window, this C code XOR operation is translated into three instructions. First, the LDR instruction reads out the current value of GPIO – > Dr register, then the EOR instruction performs XOR operation, and finally the str instruction writes into GPIO – > Dr register. It should be that the LDR read back instruction takes a long time.

Let’s look at GPIO – > Dr_ According to the results of toggle set operation and GPIO – > Dr direct write operation, it is found that the flip frequency obtained by these two methods is the same (from the assembly window, both flip methods are completed with only one STR instruction), which is 250MHz. Although the effect is good, it is a little too much, because the square wave with standard amplitude of 3.3V is not seen in the waveform (it is not sure whether it is the bottleneck of oscilloscope with 200MHz bandwidth), It is a sine wave with half amplitude (about 1.6V), and it does not rule out that the maximum running speed of pad is 200MHz. It can only ensure good voltage amplitude response performance (including turnover slope) when it is lower than 200MHz. Beyond this frequency, the waveform frequency value will not be affected, but the voltage amplitude response performance cannot be guaranteed.

In order to verify whether it is the bottleneck of the oscilloscope, ruffian Heng found a higher performance Tektronix mso5204 (bandwidth 2GHz, sampling rate 10GS / s) and retested the 250MHz signal. The results are slightly improved, but the amplitude has attenuation (2.34v), which is still limited by the pad itself.

3、 Complete result statistics

Now let’s look at all the results. Because two of the three I / O reversal methods have the same effect, we omit the results of GPIO – > Dr direct writing this method, and finally get 8 results. According to the measured results, we draw the following conclusions:

  • Summary 1: the operating frequency in pad configuration does not limit the final output flip frequency, but it can not guarantee the waveform amplitude response performance (including flip slope) after exceeding the set frequency
  • Summary 2: set GPIO – > Dr_ Toggle register for optimal I / O flip performance
  • Summary 3: the flip frequency of ordinary GPIO is about 1 / 7.5 of that of clock source IPG bus, and the limit flip frequency is 20.614mhz
  • Summary 4: the hsgpio flip frequency is about 1 / 2 of the clock source AHB bus, and the limit flip frequency is 250MHz
AHB / core clock frequency IPG bus clock frequency I / O pad configuration I / O flip method Normal GPIO limit flip frequency High speed GPIO limit flip frequency
500MHz 125MHz Fast Slew, 200MHz XOR GPIO – > Dr 5.214MHz

Standard amplitude square wave
22.946MHz

Standard amplitude square wave
500MHz 125MHz Fast Slew, 200MHz Set GPIO – > Dr_ TOGGLE 15.533MHz

Standard amplitude square wave
250MHz

Half amplitude sine wave
452.6MHz 150.8MHz Fast Slew, 200MHz XOR GPIO – > Dr 6.309MHz

Standard amplitude square wave
18.864MHz

Standard amplitude square wave
452.6MHz 150.8MHz Fast Slew, 200MHz Set GPIO – > Dr_ TOGGLE 20.614MHz

Standard amplitude square wave
226.244MHz

Half amplitude sine wave

4、 An interesting question

Finally, leave an open question, in the old article of ruffian HengTaking GPIO module as an example, talk about the standard flow of irqhandlerArm errata 838869 is mentioned in, that is, on cortex-m4 / 7, if the CPU execution speed is much higher than the GPIO peripheral register writing speed, and if the GPIO register readback is involved in the code logic, it is generally necessary to insert an additional DSB instruction after the GPIO register writing operation to ensure synchronization.

We now insert additional DSB instructions into the hsgpio flip code at the 500MHz AHB / core clock frequency to see what the impact is. As a result, the flip frequency is suddenly reduced from 250MHz to 35.8mhz.

So far, the ordinary GPIO and high-speed GPIO limit flip frequency ruffian balance on i.mxrt1010 have been introduced. Where are the applause~~~

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