Ruffian Heng embedded: in fact, the flexspi driver under i.mxrt also supports AHB mode to write nor flash


Hello, I’m ruffian Heng, a serious technical ruffian. What ruffian Heng introduced to you today isi. Under mxrt, the flexspi driver is modified to write nor flash in AHB mode

Ruffian Heng wrote an article some time agoTwo features of serial NAND flash make it unable to XIP under i.mxrt flexspi, this article introduces the page read waiting feature of NAND flash (after sending the read command, you need to read back the busy bit of the flash internal status register to judge whether the page data is ready). As a result, it can not be easily accessed through AHB like nor flash, and can only realize AHB reading in one page space (the premise is that after sending the read command in IPG mode and reading the status register to ensure that the data is ready).

Back to NOR flash, we can easily read flash data through AHB mode, but writing flash is usually realized by calling flexspi driver (i.e. IPG mode). Is it possible to also use AHB mode“Write flash in AHB mode”And? The answer is yes, but why did the ruffian Heng put a quotation mark and look down:

This paper takes the main chip i.mxrt1176 on NXP mimxrt1170-evk development board and its supporting on-board flash chip - core is25wp128 as an example.

1、 Flash write operation flow

Xincheng is25wp128 is a typical four wire QSPI nor flash, and its write (programming) timing conforms to jedec216 standard. In short, a complete write sequence includes three independent sub sequences: write enable sequence + page program sequence + read status sequence.

Let’s first look at the write enable sub timing of the leading array. The internal status register of NOR flash will have a bit called wel (write enable latch), which controls the erasure permission of flash. The default value is 0 (i.e. erasure is not allowed). If you want to write to flash, you must temporarily set the wel bit to 1 through the write enable command (this bit will automatically return to 0 after the current erase command is completed).

After wel is set, page data can be transmitted to flash. This sub sequence is page program. Page program is divided into three types according to different command addresses and data transmission modes: one-wire SPI, four wire SPI and QPI. The following is the sequence diagram of common four wire SPI. Commands and addresses are transmitted through IO0 and data is transmitted through IO [3:0].

Generally speaking, in this sequence, the incoming address should be the first address of the page, and the write data length should be a complete page size. However, it is also possible to write data with a length less than one page from the non page first address, but one thing to note is not to cross page in this sequence (if it occurs, the data exceeding the current page will be put back to the starting address of the page).

After the end of the page program sub sequence, the data has not been really written into the flash memory. The flash internal controller just starts to process the data. At this time, there will be a waiting time (about 0.2ms). There is a bit called WIP (write in progress) in the flash internal status register, which indicates the data writing status (the default value is 0. When the page program sub sequence ends, the WIP immediately jumps to 1). The user needs to read the value of the status register in real time through the read status sub sequence to know the data processing.

When the WIP bit in the flash internal status register jumps back from 1 to 0, it means that a complete write sequence is over, and the host can initiate the next write sequence.

2、 Flexspi support for write timing

Ruffian Heng’s old proseUnderstanding the lookuptable in the fdcb of i.mxrt boot head from scratchIn, the flexspi read timing is introduced in great detail, especially the implementation of AHB read support. Now ruffian Heng will introduce flexspi’s support for write timing.

The three sub sequences of flash write operations described in Section 1 are of course supported in flexspi peripherals, SEQ_ These sub timings are pre implemented in CTL components. For example, the following is the sequence of page program:

The flash write operation requires three subsequences, which is much more complex than the flash read operation single sequence, and the most important thing is that the write operation also contains an uncertain waiting period (the read status subsequence interacts with flash), which makes it impossible for flexspi peripherals to write in AHB mode, which is why flash writing is completed in IPG mode, Because in IPG mode, subsequences can be combined at will and manually scheduled by user code.

In principle, the three write operation subsequences can be placed at any sequence position in the LUT, because even if they are placed together in order, we indicate the position (index) of the first write operation subsequence in the LUT through the awrseqid bit in the flexspi – > flshxcr2 register (x can take A1 / A2 / B1 / B2, depending on the flash pin connection) The complete write operation of page data cannot be completed automatically.

But don’t give up. A separate page program subsequence can be written in AHB instead. In this way, we can also get through the addiction of writing flash in AHB. We just need to assist the write enable and read status actions in IPG mode before and after the AHB write operation. In the next section, we will use code to show you.

3、 Flexspi driver usage

Routine path: \ SDK_ 2.10.0_ MIMXRT1170-EVK\boards\evkmimxrt1170\driver_ examples\flexspi\nor\polling_ transfer\cm7\iar

3.1 initialization

Let’s take a look at the flexspi initialization function flexspi_ nor_ flash_ Init(), this function requires three configuration variables: flexspi_ config_ T-type configuration for flexspi peripheral layer flexspiconfig, flexspi_ device_ config_ T-type device configuration for flash device, deviceconfig, and very core customlut (only the timing related to flash read and write operations are listed here).

#define NOR_ CMD_ LUT_ SEQ_ IDX_ READ_ FAST_ QUAD     0

3.2 general usage (written by IPG)

Let’s first look at the flash write function in IPG mode, in which the page program sub timing is through flexspi_ The transferblocking() function is used to write the data in SRC to the IP TX FIFO with the size of 256 bytes (when flexspi – > mcr0 [atdfen] = 0 by default). Seq_ When processing, the CTL component will send all the data cached in IP TX FIFO to the flash side.

void flexspi_ nor_ flash_ program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src, uint32_t size)

3.3 special usage (written by AHB)

Now let’s modify the flash write function in IPG mode. First, modify the deviceconfig variable and point awrseqindex to pageprogram_ The position of quad in the LUT and then flexspi_ The transferblocking() function is replaced by AHB writing code (memcpy or pointer operation assignment). At this time, the data in SRC will be automatically placed in AHB TX buffer with the size of 64 bytes, SEQ_ When processing, the CTL component will send all the data cached in the AHB TX buffer to the flash side.

However, there are some limitations. According to the actual measurement, when memcpy is used for AHB writing, only the five effective lengths of 1 / 2 / 3 / 4 / 8 can be written at a time, and other data lengths are less than expected (for example, copying 5 – 7 bytes, actually only the first 4 bytes are written; copying more than 8 bytes, actually only the first 8 bytes are written), which is actually similar toSupport for AHB burst read feature by flexspi peripherals in i.mxrtRelated to the processor AHB burst strategy mentioned in the article, flexspi will only cache the AHB burst write data into the AHB TX buffer once at a time, while seq_ Each time CTL works, it will enable the data processing flow of flash device once (entering the busy state). Therefore, AHB burst is written twice in a row, and the subsequent burst behavior actually does not produce the actual flash writing effect.

flexspi_ device_ config_ t deviceconfig = {

What’s the use of writing flash in the above seemingly chicken ribs AHB way? The following ruffian Heng will talk about XECC module, and then you will know its usefulness.

So far, the introduction of transforming flexspi driver under i.mxrt to write nor flash in AHB has been completed. Where is the applause~~~

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