Hello everyone, I’m ruffian Heng, a serious technical ruffian. What ruffian Heng introduced to you today isPrecautions for downloading and starting octal flash with reverse byte order in i.mxrt under OPI DTR mode。
The official reference design boards mimxrt595-evk and mimxrt685-evk of NXP are equipped with an mx25um51345g from MXIC. This is a typical octal flash. There is nothing special about downloading and launching this flash under i.mxrt. It is fully supported in the official SDK and tool chain.
Recently, a customer selected an octal flash mx25um51245g from MXIC when designing a board. The main silk screen number is only one number different from mx25um51345g. According to the comparison of the data manual, there seems to be no much difference in function between the two. However, the customer encountered trouble when starting this flash. What’s the matter? Today, ruffian Heng came to find out:
- Note: Although the content of this article takes the i.mxrt three digit series as an example, it also applies to the i.mxrt four digit series.
1、 General octal flash reading and writing sequence design
Let’s first look at the typical mx25um51345g read-write timing design, which is very important for download and startup. As we all know, octal flash timing is mainly divided into SPI and OPI. The difference is whether command / address / data bits are transmitted only through sio[1:0] or all sio[7:0].
The following is the sequence of read and page program in SPI mode. The command and address bits are transmitted through sio, and the data bits are transmitted through sio (read) or sio (program). Here, pay special attention to the byte order of the data bits. The read and write are transmitted in positive order according to data byte 1, data byte 2, data byte 3.
Let’s take a look at the read and page program timing in OPI mode (including STR and DTR modes). Command / address / data bits are all transmitted through sio[7:0]. We also pay attention to the byte order of data bits. Reading and writing are still transmitted in the positive order of d0, D1, D2, D3.
2、 Special reading and writing sequence design represented by mx25um51245
Now let’s look at the special read-write timing design on mx25um51245g. Its timing in SPI mode and opi-str mode is no different from that of mx25um51345g (data bits are transmitted in positive order). The main differences are as follows: the timing in opi-dtr mode. We can see that the byte order on data bits during opi-dtr read-write is D1, d0, D3, D2… Such reverse order, This special byte order design is not specially reminded in the form of text in the flash data manual, but can only be observed from the sequence diagram. It is estimated that the flash manufacturer believes that the reading and writing sequence is a complete set of inversion, so the user does not need to care about this difference (that is, there is no need for the software code layer to deliberately reverse the data, and the reverse is positive).
3、 I. precautions for mxrt startup mx25um51245
From the perspective of i.mxrt startup, we can configure flexspi peripherals to access in SPI read mode or OPI read mode for octal flash. However, from the perspective of maximum performance, we usually configure opi-dtr read mode to start octal flash. Open a sample project in the mimxrt595 SDK casually, in flash_ config. C file, you can see that the read command is set to 0xEE (8dtrd).
The specific flexspi configuration is realized through the fdcb structure stored at the fixed offset of flash (that is, flash_config in the code above). The bootrom power on will first take out the fdcb from flash in the fixed 30MHz SPI read mode, then parse the fdcb to get the user specified configuration, and then make a secondary flexspi configuration to start the user program (see the old article of ruffian Heng for details)“Go deep into the initialization process of serial nor flash startup in i.mxrt1050 series ROM”）。
Have you found any problems after reading this? The fdcb and user application data in octal flash are accessed in different read timing modes of bootrom configuration. The former is through SPI read and the latter is through opi-dtr read. In this way, there may be a problem of inconsistent byte order under mx25um51245. How to solve this problem? There are three options:
4、 I. mxrt starts mx25um51245 implementation scheme
The previous section listed three solutions, of which scheme 1 has nothing to say and does not involve the unity of byte order. When using the mcubootoutility tool to download applications, do not select the specific flash model, but use the 1bit SDR mode fdcb to connect the configuration (see“Mcubootoutility v2.3 release, no flash will be missed this time”Section 2.3 of the article).
If you expect bootrom to configure flash to start in opi-dtr mode, you need to choose one of schemes 2 and 3. From the perspective of implementation efficiency, it is obvious that scheme 3 is better than scheme 2. After all, user programs often have a much larger amount of data than fdcb, and it takes longer to reverse the byte order. Scheme 3 is selected in the default download support of i.mxrt. The flash model in the mcubootoutility tool supports the mx25um51245 model throughMisc ModeThe “data order swaped” option in.
For i.mxrt500/600, its flashloader function is directly integrated into bootrom, and we can’t see the implementation source code of byte order inversion; However, i.mxrt four digit series bootrom has no download function. It is downloaded by loading secondary flashloader. Its source code is open source in \sdk\boards\evkmimxrt1xxx\bootloader_ In examples\flashloader, we can find the design of byte order inversion in the flashloader source code.
So far, the precautions for downloading and starting octal flash with reverse byte order in i.mxrt in OPI DTR mode have been introduced by ruffian Heng. Where is the applause~~~
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