Ruffian Heng embedded: compare the similarities and differences between I. mxrt and LPC in the use of RTC peripheral gpreg register

Time:2021-9-3

Hello, I’m ruffian Heng, a serious technical ruffian. What ruffian Heng introduced to you today isCompare the similarities and differences between I. mxrt and LPC in the use of RTC peripheral gpreg register

This article isApplication of GPR register that systemreset does not reset in i.mxrt1xxx in SBL project practiceAs a continuation of the article, the SBL project is designed for the i.mxrt/lpc series. The above only introduces the iomuxc without systemreset in i.mxrt1xxx_ SNVS_ For GPR register, we need to find the general register that systemreset does not reset in i.mxrtxxx and LPC.

We know that i.mxrt1xxx comes from i.MX application processor, while i.mxrtxxx comes from LPC microcontroller. It is different in origin and use. Ruffian Heng looked around in the i.mxrtxxx/lpc reference manual and finally found that the gpreg register in the RTC peripheral met the requirements. Today, ruffian Heng will take the use of this general register as an example to talk about the similarities and differences in the design of peripheral register access in i.mxrt1xxx/i.mxrtxxx/lpc:

1、 Review the design on i.mxrt1xxx

InApplication of GPR register that systemreset does not reset in i.mxrt1xxx in SBL project practiceIn this article, we find that there are two sets of registers that meet the conditions, namely iomuxc_ SNVS_ GPR and snvs_ Lpgpr, iomuxc is finally selected in this paper_ SNVS_ GPR, in the sample code, reads and writes this register directly without any extra preparation, even iomuxc_ SNVS_ GPR peripheral clock enable operation is not required.

void gpr_ rw_ test(void)

This is related to the system design of i.mxrt1xxx. In i.mxrt1xxx, CCM module is responsible for the clock switch control of all other peripherals (specifically in CCM – > ccgrx register). The following figure shows the default value of CCM – > ccgrx in i.mxrt1052 (initial value after reset, including soft / hard reset):

Each CCM – > ccgrx contains 16 2-bit cgx bits. Each cgx controls a clock switch of a peripheral. The definition of 2-bit value is shown in the table below. It can be seen that the default clocks of most peripherals are on (2’b11), and only the following three peripherals are off (2’b00):

CCM->CCGR2[CG12] - xbar2
CCM->CCGR2[CG11] - xbar1
CCM->CCGR3[CG2]  - semc

So we can read and write iomuxc at will_ SNVS_ The GPR register is because the following clock control bits are turned on by default. If this clock control bit is set to 2’b00, that is, turned off, what will happen? Ruffian Heng hung up j-link and did a read-write test. He found that when the clock is not turned on, the value of the register can still be read effectively, but the register write operation is invalid (directly ignored by the system, just like the write operation did not occur). This experience is actually different from the general MCU peripheral register read-write design,i. The access to the external address space on mxrt1xxx is not protected by the common protection mechanism on MCU (that is, when the peripheral clock is not enabled, the write access to the peripheral register should return the bus error, and the read access should return the bus error or invalid 0 value), and almost all peripheral clocks are turned on by default after reset.

CCM->CCGR3[CG15] - iomuxc_snvs_gpr

2、 Let’s look at the design on i.mxrtxxx

Now let’s take a look at the general register RTC – > gpregx that systemreset does not reset on i.mxrtxxx. We try to write this register directly in the code. It is found that the write operation does not report an error and does not take effect. The default value read back is 0. It seems that the design logic here on i.mxrtxxx is different from that of i.mxrt1xxx.

void gpreg_ rw_ test(void)

We know that clkctlx module in i.mxrtxxx is responsible for the clock switch control of all other peripherals (specifically in clkctlx – > pscctlx register). The following figure is the default value of clkctlx – > pscctlx in i.mxrt685 (initial value after reset, including soft / hard reset):

Each clkctlx – > pscctlx contains 32 1-bit xxxperipherals_ CLK bits, each xxxperipheral_ CLK controls the clock switch of a peripheral. 0 means off and 1 means on. It can be seen that most peripheral default clocks are off, and only bootrom default clocks are on:

CLKCTL0->PSCCTL0[ROM_CTL_128KB] - Boot ROM

Since gpregx is a part of the RTC peripheral, we try to turn on the RTC peripheral clock first, and then write it to the gpreg register. It is still not possible. Later, we check the RTC chapter and find that the RTC – > Ctrl [swreset] bit needs to be cleared (otherwise the RTC module is always in the reset state). Hang up j-link for a read-write test, After the peripheral clock is turned on, the register can be written normally. After the clock is turned off, the register can still be read effectively.To sum up, i.mxrtxxx does not have access to external address space as a common protection mechanism on MCU, so it is essentially the same as i.mxrt1xxx, but it does not turn on almost all peripheral clocks by default after i.mxrt1xxx is reset.

void gpreg_ rw_ test(void)

3、 Compare the design on LPC

As like as two peas, we can see that the SystemReset RTC->GPREGx is not reset at LPC. From the definition of RTC module register, it is exactly the same as RTC in i.MXRTxxx. Yes, i.MXRTxxx is not a slightest exaggeration from LPC, they are products of a platform. We tried to write this register directly in the code, and found that system errors will occur directly in both read and write operations, and online debugging cannot continue.

void gpreg_ rw_ test(void)

We know that the syscon module in LPC is responsible for the clock switch control of all other peripherals (specifically in syscon – > ahbclkctrlx register). The following figure is the default value of syscon – > ahbclkctrlx in lpc55s69 (initial value after reset, including soft / hard reset):

Each syscon – > ahbclkctrlx contains 32 1-bit xxxperipheral bits. Each xxxperipheral controls the clock switch of a peripheral. 0 means off and 1 means on. It can be seen that most peripheral default clocks are off, and only flash / FMC default clocks are on:

Syscon - > ahbclkctrl0 [flash] - flash memory

As for the preparation before operating RTC – > gpregx, it is consistent with i.mxrtxxx and will not be repeated here.Now we find that the LPC really protects the access to the external address space by the common protection mechanism on the MCU (that is, when the peripheral clock is not enabled, the write access to the peripheral register should return the bus error, and the read access should return the bus error). It is a typical MCU product, and i.mxrt actually prefers the MPU design style.

void gpreg_ rw_ test(void)

So far, comparing the similarities and differences between i.mxrt and LPC in the use of RTC peripheral gpreg register, ruffian Heng has introduced it. Where is the applause~~~

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