Hello, I’m ruffian Heng, a serious technical ruffian. What ruffian Heng shared with you today isi. Mxrt1170 XECC functional features and its way to protect serial nor flash and SDRAM。
ECC is short for “error correcting code”. ECC can check and correct errors. The memory with ECC function is generally called ECC memory. The system using ECC memory has greatly improved its stability and reliability. Compared with the previous generation i.mxrt10xx without ECC, the new generation i.mxrt1170 is fully armed on ECC, adding ECC functions from eFuse to flexram, ocram to external storage space. As shown in the following table, different types of storage are guarded by different ECC controllers:
Today, ruffian Heng will briefly introduce the XECC function on i.mxrt1170 to protect the external memory mounted on flexspi and SEMC interfaces:
1、 Introduction to XECC function
1.1 XECC features
From the user’s point of view, the design of XECC is very simple. When XECC is enabled, any AHB access to the ECC protected area (note that XECC can only be activated in AHB mode, and the IPG mode is not affected by XECC) will be taken over by XECC module. WECC component is responsible for generating ECC check values according to the data values written by the user and storing them in the target address, The RECC component is responsible for obtaining the corresponding ECC inspection value according to the address read by the user, performing inspection processing, and then returning the data value. WECC and RECC components can be controlled by independent switches.
There are three XECC modules, namely XECC_ FLEXSPI1、XECC_ FLEXSPI2、XECC_ SEMC, each module supports the setting of four ECC regions (the minimum unit of the region is 4KB, that is, the low 12bits of ecc_base / edd_addrx register is always 0).
1.2 ECC design details
For the basic concepts of ECC, seeBrief analysis of i.mxrt1170 cortex-m7 flexram ECC functional features, startup steps and performance impactSection 1.2 of is not repeated here.
1.2.1 ECC inspection capability
An ECC check value (4 bits) is calculated for every 4 bits of data in XECC. Unlike flexram, ECC has a special independent storage space for storing ECC check values. XECC check values are placed immediately after the source data, which means that XECC check values will occupy half of the ECC protected area in the target memory (flash or SDRAM).
|Storage type||ECC check data block size||ECC check value length||ECC verification capability|
|Raw NAND||512 bytes||4 bytes||5-bit error detection, 4-bit error correction|
|XECC||4bits||4bits||2-bit error detection, 1-bit error correction|
In order to facilitate the master to access through the AHB bus, the actual XECC test value is expanded to 32bits for storage, that is, the 32bits original data will be followed by the 32bits XECC test value, as shown in the figure below.
For example, XECC protects flash hung on flexspi1. The set flash ECC protection area is 0x30000000 – 0x30000fff, with a total space of 4KB. From the perspective of actual physical space (IPG reading), the original 4bytes user data (D0) is saved at 0x30000000, the 4bytes XECC check value (E0) is saved at 0x30000004, the original 4bytes user data (D1) is saved at 0x30000008, and the 4bytes XECC check value (E1) is saved at 0x3000000c
Note that the above addresses refer to the actual physical addresses, but when the master directly reads and writes flash through the AHB bus, it only needs to access 2KB of actual user data in the 0x30000000 – 0x300007ff space. It doesn’t need to care about the processing of another 2KB of XECC test value. Automatic processing and address conversion are directly performed in the SOC system, That is, 0x30000000 corresponds to the verified 4bytes user data (D0), 0x30000004 corresponds to the verified 4bytes user data (D1)
1.2.2 ECC error trigger processing
ECC errors are divided into two types: 1-bit errors and 2-bit errors (for 4bits data). From the perspective of software, 1-bit errors can be ignored, and XECC module will automatically correct them. We mainly deal with 2-bit errors. Because 2-bit errors can only detect errors and cannot be corrected, this error means that the read data is unreliable. For 1 / 2 bit errors, XECC provides interrupt response (xecc_xxmodule_int_irqn / xecc_xxmodule_fat_int_irqn).
For 32 bits data, XECC can correct 8 bits errors, but only 1 bit error can be found in each 4 bits data bit divided in sequence. If there are multiple bit errors in these 4 bits data bits and we still want to correct them, we need to use the data swap function, which will not be expanded separately. You can check RM for details.
2、 Steps to turn on XECC
2.1 activate XECC feature
When the chip leaves the factory, the XECC feature is not activated by default. If you need to enable XECC, you need to burn eFuse. 0x840  in fusemap corresponds to XECC_ Enable bit, we need to burn this bit to 1 to activate the XECC feature.
2.2 initialize memory interface peripherals
The memory interface peripherals are generally initialized before initializing the XECC module. Here, we initialize flexspi1 first, because the serial nor flash connected to flexspi1 is the default on the test board mimxrt1170-evk.
void init_ flexspi_ flash(void)
2.3 SDK driver initialization XECC
Then you can directly use the FSL in the SDK_ XECC driver initializes XECC module. The code is very simple. The following example code initializes XECC_ Flexspi1, enable the read / write ECC function of 0x30000000 – 0x30000fff area:
2.4 reading and writing ECC target area in AHB mode
The last is to useIn fact, the flexspi driver under i.mxrt also supports AHB mode to write nor flashFlexspi in Section 3.3 of the article_ nor_ flash_ Program () function to write AHB to flash to activate XECC. In order to verify whether XECC works normally, you can read back the written area with IPG and AHB respectively to see the final result.
SDK_ ALIGN(static uint8_t s_nor_program_buffer, 4);
So far, the brief analysis of the functional features of i.mxrt1170 XECC and its way to protect serial nor flash and SDRAM, ruffian Heng, has been introduced. Where is the applause~~~
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