# Ruffian Heng: an in-depth study on the alignment principle of embedded Cortex-M interrupt vector table

Time：2021-10-7

Hello, I’m ruffian Heng, a serious technical ruffian. What ruffian Heng shared with you today isCortex-M interrupt vector table alignment principle

The content of today’s article mainly comes from the discovery during the dual core startup of kinetic k32w series five years ago. Recently, a colleague happened to encounter the problem of arm Cortex-M interrupt vector table alignment, so ruffian Heng thought of it (lamented that his memory was good), turned out the email five years ago and reorganized the test results at that time.

Some time ago, the ruffian Heng just wrote an articlePrinciple of Cortex-M interrupt vector table and its redirection method, briefly introduce the working mechanism of interrupt vector table. Today, let’s talk about the alignment of interrupt vector table:

### 1、 Cortex-M interrupt vector table alignment principle

The interrupt vector table is a constant array that centrally stores the addresses of all the system interrupt handling functions (xxxirqhandler) (the function address takes up 4 bytes, so the size of each element in the array is 4 bytes). The element numbers in the table are as follows:

``1. The 0 - 1 vectors in the interrupt vector table are special, which are the initial SP and PC values of the program``

There is a special vtor register in the SCB of Cortex-M kernel (except cm0) module to control the first address of interrupt vector table. After the program runs, the user can configure SCB – > vtor register to reset the address of interrupt vector table.

The lower 7bit of SCB – > vtor register is reserved (always 0), so the first address of interrupt vector table must be aligned with 128 bytes (0x80). There is no doubt! But just 128 byte alignment? This depends on the situation, as followsCortex-M Generic User GuideThere is a paragraph (in the red box) in the description of vtor register in the manual, which means that the first address of the vector table needs to be aligned upward by 0x80 (also an integer power of 2) to cover the maximum interrupt number (xxx_irqn) actually used in the project.

• Note: for example, if the maximum peripheral interrupt actually used in the project is irq20, the minimum vector table size is (16 + 21) * 4 bytes, and the first address of the vector table needs to be aligned with 0x100 at least.

### 2、 Consequences of misalignment of Cortex-M interrupt vector table

What happens if the first address of the interrupt vector table is not aligned as specified? We find a board to measure. The selected chip is NXP i.mxrt1011, which is a MCU with cortex-m7 core. In addition to 16 system interrupts, it also contains 80 peripheral interrupts. There are 96 valid interrupts in the interrupt vector table, as shown in the startup below_ Specific interrupt response function definition in mimxrt1011. S file:

Because there are 96 interrupts in i.mxrt1011, according to the regulations, the first address of the interrupt vector table should be aligned at least by 0x200. Now we deliberately do not set the alignment according to the regulations. First select a test project \ SDK_ 2.10.0_ EVK-MIMXRT1010\boards\evkmimxrt1010\demo_ apps\hello_ World \ IAR (flexspi_nor_build), modify hello_ World. C file, plus a relocate_ vector_ The table() function redirects the interrupt vector table to new_ VECTOR_ ADDRESS：

``#define NEW_ VECTOR_ ADDRESS (0x00000080)``

Everything is ready. Now we need to enable some interrupts to verify. Ruffian Heng selects systick, lpuart1, gpt2, wdog2 and temp respectively_ LOW_ Six interrupts, high and wdog1, can be enabled from SDK \ boards \ evkmimxrt1010 \ driver_ Examples \, which will not be repeated here.

#### 2.1 test interrupt vector table aligned with 0x80

New_ VECTOR_ When address is set to the ITCM offset of 0x80, the interrupt vector table is redirected to the place aligned by 0x80, and the selected 6 interrupts are tested respectively. The final results are as follows: systick and temp_ LOW_ The interrupt responses of high and wdog1 are normal, while the interrupt functions actually responded by lpuart1, gpt2 and wdog2 are memmanage, systick and dma13. An exception occurs here.

``#define NEW_VECTOR_ADDRESS (0x00000080)``

#### 2.2 test interrupt vector table aligned with 0x100

New_ VECTOR_ When address is set to the ITCM offset of 0x100, the interrupt vector table is redirected to the place aligned according to 0x100, and the six selected interrupts are tested respectively. The final results are as follows: systick, lpuart1, gpt2 and wdog2 interrupt responses are normal, while temp_ LOW_ The interrupt functions actually responded by high and wdog1 are systick and dma10, or there are exceptions.

``#define NEW_VECTOR_ADDRESS (0x00000100)``

#### 2.3 test interrupt vector table aligned with 0x180

New_ VECTOR_ If address is set to the ITCM offset of 0x180, the interrupt vector table is redirected to the place aligned by 0x180, and the measured effect is consistent with Section 2.1.

``#define NEW_VECTOR_ADDRESS (0x00000180)``

#### 2.4 test the interrupt vector table aligned with 0x200

New_ VECTOR_ If address is set at the ITCM offset of 0x200, the interrupt vector table is redirected to the place aligned according to 0x200, and the six interrupts can respond normally. After all, they comply with the alignment provisions in the arm manual.

``#define NEW_VECTOR_ADDRESS (0x00000200)``

#### 2.5 summary of test results

Because i.mxrt1011 has only 96 valid interrupts at most, some alignment tests cannot be completely covered. PI Ziheng then tested it again on i.mxrt1176 (234 valid interrupts at most), and finally summarized the following phenomena:

``1. When the interrupt vector table is aligned with 0x80:``

### 3、 Wonderful use of Cortex-M interrupt vector table misalignment

What is the significance of the test results of the misalignment of the interrupt vector table in Section 2? In fact, there are. We can use this result to reduce the size of the interrupt vector table, which will be helpful for optimizing the code size when developing applications on some MCU with small flash capacity. The following ruffian Heng will write an article specifically.

So far, the Cortex-M interrupt vector table alignment principle has been introduced. Where is the applause~~~