Read priority and sram-mram hybrid architecture


Because of its many advantages, MRAM has the potential to replace SRAM and DRAM. MRAM memory constructed with MTJ memory cells can be used as cache. However, the long latency and high power consumption of MRAM write operation become its bottleneck, which hinders the further improvement of its performance. Read first write buffer and sram-mram hybrid architecture can improve the performance of MRAM and reduce its power consumption.


Read priority and sram-mram hybrid architecture

Replacing SRAM with MRAM may result in performance degradation. Therefore, two strategies are proposed to alleviate this contradiction: one is to introduce read first write buffer; the other is to introduce sram-mram hybrid structure. The two can be combined to improveMRAMThe performance of the cache.


Read priority write buffer

Because L2 cache obtains commands from upper level memory and write buffer, there must be a priority policy to solve the conflict between read and write commands. For MRAM cache, the write delay is much larger than the read delay, so the write operation should be prevented from blocking the read operation.


Two rules are proposed to ensure the priority of read operation

(1) Read operations always have priority over write operations.


(2) When the write operation blocks the read operation and the write buffer is not full, the read command can abort the current write operation under certain priority conditions. Then read the command to get execution power. The aborted write operation will be retried later. When the completion degree is lower than α, the read command will not get priority. The simulation results show that α is 50%, which can meet various working conditions. To implement this strategy, a counter is needed, starting from O when writing begins. The cache controller checks the counter and then decides whether to abort the current write operation to perform the read operation. Compared with the scheme of directly replacing SRAM with MRAM, this strategy eliminates the performance degradation, but increases the power consumption, because some write operations need to be re executed.


L2 cache of sram-mram hybrid architecture

Researchers propose to replace pure MRAM memory with sram-mram hybrid structure, in which SRAM accounts for only a small part. Its main purpose is to concentrate the write operations on SRAM and reduce the number of write operations in MRAM.

Figure 1 sram-mram hybrid structure


As shown in Figure 1, the researchers reduced part of MRAM and replaced it with MRAMsramAnd all SRAM units are put together to build a number of complete SRAM groups on the processor layer. The SRAM group is placed in the center of the processor layer instead of scattered, so that the area of the processor layer will increase and the area of the cache layer will decrease.


Several management strategies of hybrid structure are given

(1) The cache controller needs to know the location of SRAM and MRAM. When there is a write error, the controller gives priority to put the data into SRAM.

(2) Considering the possibility that the processor writes data to some units repeatedly, if the data is in MRAM, it needs to be moved into SRAM. If data goes through two consecutive write operations, the data needs to be moved into SRAM.

(3) Note that the processor’s read operation may also cause data transfer, and its number of times may be greater than the write operation. Therefore, a new data mobility strategy is introduced. For the traditional management strategy, the data will be moved to the host group, while the mixed structure strategy will move the data into SRAM.

(4) The results show that the performance of the hybrid structure is improved by 5.65% on average, and the average total power consumption is reduced by 12.45%.