1Function and overview of bus
Solve the communication problem between devices.
Bus is to solve the communication problem between different devices.
The bus can connect CPU and IO devices.
2Bus classification: on-chip bus and system bus
On chip bus: bus connecting internal cache, register and operation unit of CPU;
data bus: bidirectional transmission of data information of various components; The number of bits (bus width) of the data bus is an important parameter of the data bus (generally the same as the number of bits of the CPU)
If the bus is 32 bits, it can transfer 4 bytes of data at a time. If the bus is 64 bits, it can transfer 8 bytes of data at a time
Address bus: specify the address of source data or destination data in memory; The number of bits of the address bus is related to the storage unit
(number of bits of address bus = n, addressing range 0 ~ 2 ^ n-1)
Control bus: control bus is a transmission line used to send various control signals;
The control signal is sent from one component to another via the control bus;
The control component can monitor the status between different components (ready / not ready);
3President of bus: in order to solve the conflict of bus use right.
There are three arbitration methods. (chain query, timer timing query, independent request)
In order to solve the problem of bus use right between devices;
Chain query:Each device is connected in series with the arbiter. When a device applies for bus use right, the arbiter issues the use license and always receives the signal according to the priority of the device, so that the device with high priority can always obtain the use right first.
Advantages and disadvantages of chain query:
Advantages: low circuit complexity and simple operation mode
Disadvantages: it is difficult for devices with low priority to obtain the right to use the bus
Disadvantages: sensitive to computer failures
Timer timing query:The arbitration controller labels the equipment and uses the counter to count. Secondly, when the controller receives the arbitration signal, it sends the count value to all equipment. When the count value is consistent with the equipment number, it will give priority to obtain the use right.
Working process of timer query: the device is mainly compared with the counter through the device address. The course uses the counter for convenience of understanding. It can be understood that the device has a unique device address. Compare the value of the device address with the counter. If it is consistent, the bus use right will be obtained.
Independent request: each equipment has a vertical line independent connection arbiter, which can send and receive requests to the arbiter independently. When multiple request signals are received at the same time, the arbiter has the right to assign the use right according to priority.
Advantages and disadvantages of independent request:
Benefits: fast response speed, and the priority can be changed dynamically
Disadvantages: many equipment connections and complex bus control
Input and output equipment of computer
Common input and output devices：
Character input device: keyboard (membrane keyboard, mechanical keyboard).
Image input device: mouse; Digital plate; Scanner.
Image output device: display (CRT display, LCD display); printer; Projector.
General design of input / output interface：
data line: transmission line (unidirectional and bidirectional) for data exchange between IO equipment and host.
State line: signal line of IO device status reporting to the host (whether it is normally connected; whether it is occupied).
Command line: signal line for CPU to send command to equipment (send read-write signal; send start stop signal).
Equipment selection line: the host selects the signal line of IO equipment for operation. (select the connection to the device bus)
CPUAndIOCommunication method of equipment (program interruptionDMA）：
premise: CPU speed and IO device speed are inconsistent
Program interrupt: when the peripheral equipment is ready, it sends an interrupt to the CPU, and the special circuit corresponding interrupt signal.
It provides an asynchronous way for low-speed devices to notify the CPU. The CPU can run at high speed while taking into account the response of low-speed devices
The first method will reduce the efficiency if the CPU is interrupted frequently.
Therefore, a second method, DMA direct memory access method, is produced:
DMA: DMA (direct memory access). In the case of no DMA, the CPU may need to be frequently interrupted by the IO device, and the CPU will copy the data between the IO device cache and the main memory, which takes up a lot of CPU time. In the case of DMA, when the IO device is ready, it will notify the CPU first, and then the subsequent data transmission can be completed with the assistance of DMA, without the participation of CPU.
The emergence of DMA is to solve the problem of batch data input / output. DMA refers to the interface technology that external devices directly exchange data with system memory without CPU. In this way, the transmission speed of data depends on the working speed of memory and peripherals.
Usually, the system bus is managed by the CPU. In DMA mode, the CPU is expected to let these buses out, that is, the line connected to these buses by the CPU is in the third state (high resistance state), and the DMA controller takes over, controls the number of bytes transmitted, judges whether DMA ends, and sends DMA end signal.
Therefore, the DMA controller must have the following functions:
1. It can send system hold signal to CPU and put forward bus takeover request;
2. When the CPU sends the signal of permission to take over, it is responsible for controlling the bus and entering the DMA mode;
3. It can address the memory and modify the address pointer to read and write the memory;
4. It can determine the number of bytes of this DMA transfer and judge whether the DMA transfer is overnight.
5. Send DMA end signal to restore the CPU to normal operation
Overview of computer memory
Classification of memory
Pressstorage medium classification
- Semiconductor memory: memory, U disk, solid state disk, etc
- Magnetic memory: magnetic tape, magnetic disk, etc
- Random access memory (RAM): random read, location independent
- String memory: location related, sequential search
- Read only memory (ROM): read only, no write
Reading and writing speed
Capacity + price = > bit price: price per bit
cacheHigh speed: high price
Main memory: moderate speed, moderate price
Supplementary depositLow speed: low price
cache–Main memory hierarchy
When the CPU accesses memory, eitherAccess instructionstillAccess data, all the storage units accessed areTends to gather in a small continuous area
realization:Add a layer of cache with fast speed and small capacity between CPU and main memory
objective: solve the problem of insufficient main memory speed
Main memory–Auxiliary storage level
principle: principle of locality
realization: add auxiliary memory (disk, SD card, USB flash disk, etc.) in addition to main memory
objective: solve the problem of insufficient main memory capacity
Main memory and sub memory of computer
working principleThrough RAM (random access memory):capacitanceThe stored data must be refreshed every other period of time. If the power is off, all data will be lost after a period of time.
Memory andCPUInteraction of:
Relationship between operating system bits and memory size
First, 2 comes from bits. One bit can represent 0 and 1.
Then, for 32-bit addresses, there is an addressing range to the power of 2 ^ 32, which is converted to the power of 4 * 2 ^ 30, which refers to the addressing range. Each address is addressed by word as 1byte, so the overall process is 4 * 1024 * 1024 * 1024 * 1byte = 4G.
32-bit CPU means that one CPU addressing can address addresses with a length of 32 bits, that is, up to 2 ^ 32 data addresses. For each address, the addressed data size is a byte 1byte, and 4G results can be obtained; Therefore, for 32-bit CPUs, installing more than 4G of physical memory is a waste.
working principle: the surface is a hard magnetic material that can be magnetized. The moving magnetic head moves radially to read track information.
Main algorithms of disk content reading
- First come first serve algorithm
- Shortest seek time first
- Scanning algorithm (elevator algorithm)
- Cyclic scanning algorithm
Examples: if the outermost track of the disk is 1 and the innermost track is 5, the magnetic head is now in track 4, and the magnetic head moves outward, find the moving order of the magnetic head of different seek algorithms, assuming that the order of the magnetic head to be read is 142315
First come first serve algorithm（FCFS）: track read and write requirements for sequential access processes. The reading order is 142315
Shortest seek time first algorithm（SSTF）: it is related to the current position of the head. Priority is given to the track closest to the head. The reading order is 452311
Scanning algorithm (elevator algorithm)/SCAN）：Only move in one direction at a time, and move in the opposite direction after reaching the end of one direction. The reading order is 432115
Cyclic scanning algorithm（C-SCAN）: move in one direction only. The reading sequence is 451123
How cache works
Method of accessing data in main memory of premise knowledge：
1. word: refers to the combination of binary codes stored in a storage unit
2. Word block: a group of words that are stored in consecutive storage units and are regarded as a unit
Examples: assuming that the user space capacity of main memory is 4G, the word block size is 4m and the word length is 32 bits, what should be the number of bits of block address m and intra block address B in the word address?
The internal storage structure of cache is very similar to the logical structure of main memory. The buffer capacity is small and the buffer speed is faster
CPUData can be obtained from cache and main memory, and the former is more efficient than the latter.
- Hit rate is an important performance index to measure cache
- Theoretically, when the CPU can access data from the cache every time, the hit rate is 1
Assuming that the CPU accesses the cache 2000 times and the main memory 50 times when executing a certain program, it is known that the access time of the cache is 50ns and the access time of the main memory is 200ns. Calculate the hit rate, access efficiency and average access time of the cache main memory system.
solution: the hit rate, access efficiency and average access time are 0.97, 91.7% and 54.5ns respectively
Cache replacement strategy
Replacement timing: if there is no data to run in the cache, the data will be taken from the main memory.
Replacement algorithm: random algorithm, first in first out algorithm（FIFO）The least frequently used algorithm（LFU）. least recently used algorithm（LRU）
- Random algorithm（RAND）: every time a replacement occurs, randomly select a cache location, and then replace the relevant contents
- First in first out algorithm（FIFO）：The cache is regarded as a first in, first out queue, giving priority to the replacement of the first incoming word block
- Least frequently used algorithms（LFU）：Priority is given to eliminating the least frequently used words, which requires additional space to record the frequency of word blocks
- Least recently used algorithm（LRU）：Give priority to the elimination of word blocks that have not been used for a period of time; There are many implementation methods, generally using two-way list; Put the current access node in front of the linked list (ensure that the head node of the linked list is the most recently used)
Computer instruction system
Form of machine instructions
Machine instructions are mainly composed of two parts: operation code Address code
Operation code: the operation code indicates the operation to be completed by the instruction; The number of digits of the operation code reflects the operation type of the machine (for example, if there are 8 digits, then 2 ^ 8 = 256 operations)
Address code: directly give the operand or the address of the operand; branchThree address instruction、Two address instructionandOne address instruction、Zero address instruction
Three address instruction:
II. Address instruction:
I. address instruction:
Zero address instruction:
Operation type of machine instruction (data transmission, arithmetic logic operation, displacement operation, control instruction)
1. data transmission
- Transfer between registers, between registers and storage units, between storage units (storage units can be main memory, cache, hard disk, etc.)
- Data reading and writing, address data exchange, reset, etc
2. Arithmetic logic operation
- Addition, subtraction, multiplication and division between operands
- And or non equal logical bit operation of operands
3. Operation displacement
- Shift data left (2), divide data right (2)
- Complete the necessary operations of data in the arithmetic logic unit
4. Control command
- Waiting, shutdown, idle operation, interruption, etc
Addressing mode of machine instructions (instruction addressing, data addressing)
Instruction addressing (sequential addressing, skip addressing)
1. Sequential addressing:The address of the next instruction is automatically formed by adding 1 to the program counter PC
2. Skip addressing:Realized by transfer instruction。
Data addressing (immediate addressing, direct addressing, indirect addressing)
1. Immediate addressing:Machine instructions contain operational data without access to memory
2. Direct addressing:The machine instruction contains the address of data in memory, and there is no need to calculate the data address
3. Indirect addressing:The machine instruction contains the address of the data address in the memory, and the real data can be found through the memory address. You need to access main memory one or more times to get operands
Advantages and disadvantages of data addressing
The controller coordinates and controls the operation of the computer
- The address used to store the next instruction
- The loop takes instructions from the program counter
- When the instruction is taken out, it points to the next instruction
- In the field of electrical engineering, it is used to send timing pulses
- The CPU works rhythmically according to different timing pulses
- It is one of the main components of the controller
- Computer instructions are composed of operation code and address code
- The operation corresponding to the translation operation code and the data corresponding to the control transmission address code
- It is also one of the main components of the controller
- Fetching computer instructions from main memory or cache
Main memory address register：
- Save the address of the unit that the current CPU is about to access
Main memory data register：
- Save the main memory data that the current CPU is about to read or write
General purpose register：
- Temporarily storing or sending data or instructions
- The intermediate results of ALU operation can be saved
- The capacity is larger than that of general professional registers
Computer arithmetic unit
Arithmetic unit is used for data operation and processing
data cache ：
- It is divided into input buffer and output buffer
- The input buffer temporarily stores the data sent by the peripheral
- The output buffer temporarily stores data sent to peripherals
- Alu: arithmetic logic unit, which is the main component of arithmetic unit
- Common bit operations (shift left and right, and, non)
- Arithmetic operation (addition, subtraction, multiplication and division)
Status word register：
- Storage operation status (condition code, carry, overflow, result positive and negative, etc.)
- Store operation control information (debugging tracking flag bit, allowable interrupt bit, etc.)
General purpose register：
- Used to temporarily store or transmit data or instructions
- The intermediate results of ALU operation can be saved
- The capacity is larger than that of general special registers
CPUThe process of instruction execution
Because it’s incpuExecuted within,So the equipment involved are: controller(Program counter,Instruction decoder,sequence generator,Instruction register)
Cache(data cache ,instruction buffer ),Arithmetic unit(General purpose register,Data register,Status register),They are connected by an on-chip bus;
The detailed process is:
Firstly, when the system operator calls the system function, it will generate instructions and data, and then they are cached into the instruction cache and data cache (for example, the data cache has “address” 1, data 120;
The instruction cache has address 101, operation code MOV, address code RO, R1), and then the program counter will record the address of the instruction in the instruction cache (e.g. 101). The instruction will be transmitted to the instruction register (operation code, address code) through the on-chip bus, and then sent from the instruction register to the instruction decoder. Then the program counter will + 1 (e.g. 102), and then the instruction decoder will complete decoding (turning assembly language into machine language), Then it sends a control signal to the arithmetic unit through the on-chip bus for operation:
For example, R1 in the data of address 101, operation code MOV, address code R0 and R1 in the instruction cache is loaded into Alu (arithmetic logic unit, which is a logic gate), and then transmitted to the data buffer through the data bus of the on-chip bus. Then, the R1 data is overwritten with R0, the operation status (status register) is recorded and the operation result is sent to the UI. So far, the operation of this instruction is completed, and the CPU will execute the next instruction (if any operation is initiated)
CPUPipeline design of
In the process of execution, the controller and arithmetic unit cannot work at the same time, so the comprehensive utilization of CPU is not high, so pipeline design is needed
It can be seen that in the case of non pipeline, instructions can only be executed one by one, while in the case of pipeline, the system can execute instructions concurrently (the latter instruction can be executed before the previous one ends), which greatly increases the execution efficiency