Piziheng embedded: Using GPR register of systemreset in i.mxrt1xxx in SBL project

Time:2021-7-20

Hello everyone, I’m a ruffian Heng. I’m a serious technical ruffian. Today, ruffian Heng introduces to youi. The small magical use of GPR register in mxrt1xxx that systemreset does not reset

We know that the code design of a slightly large-scale project is usually completed by many people. At the beginning of the overall design of the project, the project leader usually divides the code according to the function. The codes of each function block should be as low as possible, independent of each other and have no influence on each other, so that each function can be tested independently and the project can be developed in parallel, In the later stage, the function block can be integrated through the pre-defined interface / protocol.

However, in embedded software projects, the above methods sometimes encounter the problem of mutual interference after function block integration, because embedded projects are often not pure software design, but also deal with on-chip and off-chip resources, and on-chip and off-chip devices belong to the category of hardware, and the work of hardware modules depends on the state before and after (this is especially obvious in the configuration of on-chip clock), When something goes wrong, the traditional method is to analyze and solve it one by one. However, any code changes or the addition of new features may bring new potential interference problems.

So, is there a solution to this dilemma once and for all? In fact, there are! That is, each function block should not rely on the initial state of the chip when it is designed. It should clean up the system environment when it enters, then do the function design, and do the system recovery when it exits. Although this method is safe, it will lead to the problem of inefficient operation of the whole project after integration. Today, PI Ziheng is going to introduce a method to solve the problem of mutual interference in the integration of mutually exclusive function code blocks by using GPR register which is not reset after system reset in I. mxrt chip.

1、 Pain points in SBL project

Recently, NXP MCU se team has been working overtime to catch up with a big project, which is created for customer product OTA needs. We know that online upgrade is an unavoidable topic for every intelligent product. In order to facilitate customers to upgrade products based on i.mxrt/lpc online, NXP se team specially introduces OTA reference design. The following is the functional architecture diagram: the project is divided into two parts: SBL and SFW. SBL is responsible for ISP local update (UART / USB) and app switching management; SFW is an example app. In addition to the customer project business function, it also integrates the remote update function (WiFi, Ethernet, USB flash disk and SD card).

In SBL code design, there are two main sub function modules: one is ISP local update (ISP)_ boot_ The other is app switch management (SBL)_ boot_ ISP local update is optional, while app switch management is required.

The main process of SBL is to execute ISP local update function block after power on and running. If ISP command is received from host within the timeout period, it will enter ISP command processing. After that, it will not exit ISP unless ISP reset command or board level reset is executed;

If the ISP command is not received within the timeout period, go to the app switch management function block. When verifying the app, if there is a legal app in flash, jump to the past execution; If no legitimate app is found, it will return to ISP for local update (infinite timeout at this time). The main logic code is as follows:

#define COMPONENT_ MCU_ ISP

In the above SBL design, you will find that ISP local update and app switch management are mutually exclusive in execution, and it is the APP processing requirements in flash that link them together. From the perspective of software integration, these two functions should not have influenced each other, but actually they have influenced each other, because they did not follow the principles of cleaning up the system when entering and restoring the scene when exiting, so ISP is very difficult_ boot_ Main() jumps to SBL after the timeout_ boot_ Main () has an impact on some of its signature verification functions, while SBL_ boot_ After main() is executed, no legal app is found, and it jumps back to ISP_ boot_ The ISP function is abnormal again when using main(). We need to solve this problem.

2、 Finding the ideal GPR register in i.mxrt

The problems described in the first section can be solved by restoring the scene when the function block exits. However, the amount of code for each module is large, so it is not easy to restore the scene one by one by using the code. Ruffian Heng thought of a good way is to call NVIC_ Systemreset() function to simply and rudely reset the chip system, what we need to do is to find an area that can temporarily store the flag bit, and the content of this area is not affected by the soft reset of the system. After the chip is reset, the judgment processing of the flag bit is added in SBL, and the flag bit is cleared after the processing.

Before looking for this area that is not affected by the soft reset of the system, we first have a basic understanding of the power management architecture in I. mxrt. The figure below shows the power architecture of i.mxrt1060. In addition to the special power supply requirements of USB and ADC modules, the chip has four kinds of power input. In board level power supply design, VDD is usually used_ SNVS_ In requires a single external input (battery powered by design), and the other three power supply VDD_ HIGH_ IN / DCDC_ IN / VDD_ SOC_ In can share one external input (chip POR)_ The B pin is often connected to this external input control.

VDD_ HIGH_ In: power the LDO inside the chip

According to the level of chip system reset, there are three types of reset: the first is the support of sysresetreq reset integrated in the air register of SCB module of cortex-m7 kernel, and the second is the power on of DCDC (POR)_ B reset), the third type is the overall power on. According to the three different degrees of reset, PI Ziheng sorted out all the areas on I. mxrt that can store the flag bits. The influence of different reset types is as follows:

Module / reset type NVIC_SystemReset() POR_ B and DCDC power on again Power on again as a whole
TCM


OCRAM


IOMUXC_GPR


SRC_GPR
keep reset reset
IOMUXC_SNVS_GPR


SNVS_LPGPR
keep keep reset
Flash, eFuse keep keep keep

According to the above table, we first exclude flash and eFuse with NVM attributes, which do not meet the requirements of temporary storage and easy reading and writing. TCM / ocram is available, but need to do special processing in SBL project, allocate a. Noinit area, and make sure bootrom does not use this area, it is still a bit troublesome. IOMUXC_ GPR / SRC_ GPRS are easy to use, but they have been occupied by SoC / bootrom, so they can’t be used casually, and the impact on the chip is unknown. IOMUXC_ SNVS_ GPR / SNVS_ Lpgpr is good for both, but the latter is sometimes used to store user keys when encryption is enabled. So iomuxc_ SNVS_ GPR register is the best choice, which is also the GPR register open to users.

3、 Using GPR register in SBL project

Now we have the ideal iomuxc_ SNVS_ GPR register, then two functions ISP can be added to SBL code_ cleanup_ enter()、isp_ cleanup_ The former is used to trigger the mark state before soft reset, and the latter is used to read the mark state after soft reset for corresponding processing. The final modified SBL main logic code is as follows:

#define CLEANUP_ ISP_ TO_ SBL (0x5A)

At this point, i. mxrt1xxx system reset GPR register does not reset the small magical use of ruffian balance will be introduced, where is the applause~~~

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