PI Ziheng embedded: I. similarities and differences between the definition of AHB master ID of flexspi peripheral and the designation of AHB RX buffer under the full series of mxrt


Hello, I’m ruffian Heng, a serious technical ruffian. What ruffian Heng introduced to you today isi. Similarities and differences between AHB master ID definition of flexspi peripheral and AHB RX buffer specification under mxrt full series

Because the full range of i.mxrt models do not contain internal flash (except for some SIP versions), flexspi peripherals used to connect external nor flash are particularly favored. In order to improve the in-situ execution efficiency of code in flash, the NXP design team has given the prefetch feature to flexspi to accelerate access efficiency (cache data with AHB RX buffer).

Ruffian Heng wrote a measured article on prefetch effect beforeAHB read access under flexspi peripherals (with prefetching), the article only covers the simplest application scenario, that is, a single AHB RX buffer occupies all RX buffer space and only serves a single AHB master – CPU. In the actual project, multiple AHB masters may AHB read and access flash, which extends today’s theme:

1、 AHB master and AHB RX buffer

i. The AHB master on mxrt series includes up to 16 core, DMA, encryption modules, etc. these masters have the ability to actively initiate AHB read access to flash. In order to better serve these masters, there are more than one AHB RX buffer on flexspi for storing prefetched data, generally 4 / 8. Users can freely allocate the size of these AHB RX buffers as needed (the total size is certain, usually 1 / 2KB), and can assign an AHB RX buffer to a specific master for exclusive use.

  • Note: I. The mxrt series does not support assigning multiple AHB RX buffers to the same AHB master. In fact, this requirement can be realized by configuring different AHB RX buffer sizes.

The following is a summary of AHB RX buffer on the full range of i.mxrt models:

i. Mxrt model Number of flexspi peripherals Number of AHB RX buffers on a single flexspi Total size of AHB RX buffer on a single flexspi
i.MXRT1011 1 4 1KB
i.MXRT1015 1 4 1KB
i.MXRT102x 1 4 1KB
i.MXRT105x 1 4 1KB
i.MXRT106x 2 4 1KB
i.MXRT116x 2 8 2KB
i.MXRT117x 2 8 2KB
i.MXRT5xx 2 8 FlexSPI0: 1KB

FlexSPI1: 2KB
i.MXRT6xx 1 8 2KB

The benefits of multiple AHB RX buffers are obvious. Compared with a single AHB RX buffer, it can effectively avoid the inefficient situation of AHB RX buffers being continuously cleared and re cached due to frequent alternate access to flash by different AHB masters.

2、 AHB master ID definition

2.1 i.MXRT10xx

On i.mxrt10xx, AHB masters are divided into four categories in the following table (which can be allocated to four AHB RX buffers). Except for core, EDMA and DCP, other masters are directly packaged together (cannot be split). The master ID value is represented by 4bit.

2.2 i.MXRT5xx/6xx

On i.mxrt5xx, the master ID value is also represented by 4bit, but the AHB masters are further subdivided into eight categories (which can correspond to eight AHB RX buffers one by one). As shown in the table below, the main last category of Axi: AHB bridge is packaged (including GPU, lcdif, etc.). In addition, flexspi0 / 1 on this model is not completely equivalent, so their respective master ID definitions are also different.

On i.mxrt6xx, the definition of master ID is not found in the user manual of rev1.4. It needs to be updated. Blind guessing is similar to the definition under i.mxrt5xx flexspi1. However, there is no smartdma peripheral on i.mxrt6xx, so it needs to be verified.

2.3 i.MXRT11xx

On i.mxrt11xx, the master ID value is represented by 16bit, and AHB masters have their own ID definitions without any native packaging, as shown in the table below. This series is a new architecture. It introduces remap technology in ID design. This remap technology allows users to package multiple masters together and assign them to the same AHB RX buffer. In this way, 17 masters can be assigned to 8 AHB RX buffers.

3、 AHB RX buffer assignment

To use the AHB RX buffer normally, you must ensure that the prefetch function of the flexspi peripheral is on, that is, only when the prefetchen bit in the following registers is enabled. Each AHB RX buffer has a separate configuration register (ahbrxbufxcr0).

Flexspi - > ahbcr [prefetchen], master prefetch switch

3.1 i.MXRT5xx/6xx/10xx

i. The master ID in mxrt5xx / 6xx / 10xx is represented by 4 bits, and their AHB RX buffer is specified in flexspi – > ahbrxbufxcr0 [mstrid].

3.2 i.MXRT11xx

i. The master ID in mxrt11xx is represented by 16 bits, so the flexspi – > ahbrxbufxcr0 [mstrid] bit is actually invalid (i.e. reserved state). Their AHB RX buffer should be specified in the following flexspi – > hmstrxcr register, but first, the master ID remap function must be enabled (hmstridremap = 1, this bit is not recommended to be set to 0).

Flexspi - > ahbcr [hmstridremap], master ID remap switch

So far, the similarities and differences between the definition of flexspi peripheral AHB master ID and the designation of AHB RX buffer under the full series of i.mxrt have been introduced. Where are the applause~~~

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