High density MRAM has very low power, high read speed, very high data retention and durability, which is suitable for a wide range of applications. The unit area is only 0.0456 square micrometer, the reading speed is 10ns, the reading power is 0.8ma/mhz/b, and the leakage current is less than 55mA at 25C in low power standby mode (lpsb), which is equivalent to only 1.7e-12a per bit. It has a durability of 100k cycles for 32MB data and > 1m cycles for 1MB data. It has a 90 second data retention capability under 260 ° C IR refluxing, and can store data for more than 10 years at 150 ° C.
MRAM read operation
In order to wake up fast and low energy consumption from LPSM to achieve high-speed read access, it uses a fine-grained power gating circuit (one per 128 lines) and wakes up in two steps (as shown in Figure 1). The power switch consists of two switches, one is used for chip power VDD, the other is used to supply vreg stable voltage from LDO (low drop out) regulator. Firstly, the VDD switch is turned on to pre charge the power line of the WL driver, and then the vreg switch is turned on to raise the level to the target level, so as to realize the fast wake-up of < 100ns and minimize the transient current from vregldo.
MRAM write operation
MRAM write operations for low resistance RP and high resistance rap require bidirectional write operations as shown in Figure 2. To write rap status to RP, BL should be offset to VPP and WL to vreg_ W0, SL to 0 to write 0 state. To write the 1 state, changing rap to RP requires the current in the opposite direction, where BL is 0, SL is VPP, and WL is vreg_ W1。
In order to achieve a retention time of 90 seconds in IR reflow at 260 ° C, MTJ with high energy barrier EB is required. This requires increasing the MTJ switch current to hundreds of Ma required for reliable writing. After temperature compensation, the charge pump generates a positive voltage for the selected cell and a negative voltage for the unselected word line to suppress the bit line leakage at high temperature. The write voltage system is shown in Figure 3.
When working in a wide temperature range, it is necessary to compensate the writing voltage. Figure 4 shows the shmoo plot of the write voltage from – 40 degrees to 125 degrees, where f / P indicates failure at – 40 degrees and passage at 125 degrees.
The BIST module with standard JTAG interface can realize self-healing and self-regulation to simplify the test process. The memory controller TMC of dual error correcting ECC (dececc) shown in Fig. 5 is implemented.
TMC implements intelligent write operation algorithm, which realizes offset setting and verification / retrying time to achieve high write durability (> 1m cycles). It includes read before write (used to determine which bits need to be written) and dynamic packet write (used to improve write throughput), multi pulse write operation with write verification, and optimized write voltage for high durability. The algorithm is shown in Figure 6.
MRAM data reliability
In many applications of spin based STT-MRAM, magnetic interference is a potential problem. The solution is to deposit a 0.3mm thick magnetic shielding layer on the package, as shown in Fig. 6. The experiment shows that the bit error rate can be reduced from > 1e6ppm to ~ 1ppm when the magnetic field strength of commercial wireless charger of mobile device is 3500oe. In addition, the data can be stored for more than 10 years at a magnetic field of 650 OE at 125 ° C.