Let’s look at the effect first
74HC595 is a commonly used serial to parallel chip, which supports chip cascade to realize the function of a small number of IO ports controlling the output of multiple IO ports
Pin 14: DS, serial data input pin
Pin 13: OE, output enable control pin, it is low power to enable output, so it is connected to GND
Pin 12: STCP, memory register clock input pin. At the rising edge, the data is transferred from the shift register to the tape storage register.
Pin 11: SHCP, shift register clock pin, when the rising edge, the bit data in the shift register moves backward as a whole and accepts a new bit (input from Ser).
Pin 10: MR, at low level, clear the existing bit data in the shift register. Generally, it is not used. It can be connected to high level.
Pin 9: q7s, serial data outlet pin. When the data in the shift register is more than 8 bits, the existing bits will be “squeezed out”, which is from here. Cascade for 595.
Q0 ~ Q7: parallel output pin
If we want to realize data transmission, we can realize it according to the following logic. Each dial switch is connected with a pull-down resistor, so when the dial switch is not on, it is equivalent to a low level
Step 1: pin 12: STCP outputs low level. In the example, the dial switch 2 is turned downward
Step 2: pin 14: DS. If the data bit does not need to be changed, the dial switch 1 does not care. When you dial down, the data bit is 0 and when you dial up, it is 1
Step 3: pin 11: SHCP. In the example, the dialing switch 3 is low level first and then high level, which is equivalent to dialing down and then up
Step 4: pin 12: STCP outputs high level. In the example, the dial switch 2 is turned upward
This is a complete data transmission decomposition. Let’s continue the operation. I let the rear four lights go out, and the front four lights are equivalent to the transmission data 0x0f, and the binary is 000 1111
Manual decomposition can be realized, so what if it is controlled by single chip microcomputer? You can start to realize… ✌