Interface between 65nm SRAM of cypress and ASIC / FPGA / controller

Time:2021-4-1

Cypress aims to grow faster than any semiconductor industry in the automotive, industrial and consumer electronics markets. In security wireless technology, together with MCU, memory, analog IC and USB controller, it provides obvious competitive advantages for the field of Internet of things, and has made great leaps in emerging markets, including networking equipment and autonomous driving vehicles. Cypress provides driver, routine and necessary FAE support and other product services on behalf of Yuxin electronic support.

 

System designers can use err pin to monitor the integrity of data in SRAM. Only ifSRAMThe err signal is declared only when a bit error is detected and corrected, so it is recommended to pull down the signal weakly to avoid intermediate voltage level during write operation or when SRAM is disabled. In the write cycle or chip disable cycle, err pin is in Hi-Z state.

 

1. Connecting err pin

Cypress SRAM without err pin can be connected in the system like traditional SRAM. For SRAM with err option, the system designer needs to connect the err pin correctly in the system. If the err pin is not used in the system, it can be left on. This section describes how to use SRAM to connect err pin in three basic cases.

· systems with a single SRAM

Width expansion

Deep expansion

 

1.1 system with single SRAM

In the system where only one SRAM device is connected to the on-board controller / ASIC / fpga4, the err pin can be connected to the GPIO / interrupt pin of the ASIC. In each read cycle, the controller can monitor the output of err pin. When a high level on the err pin is detected, the ASIC should start a software subroutine to rewrite the correct data read from the SRAM. Figure 6 shows the architecture of this solution.

 

1.2 width expansion

The new generation controller has 32-bit data interface. In this kind of application, the system designer can use two pins with err pinCYPRESS65 nm SRAM to extend the data bus width. The system software must monitor the two err pins separately. The system designer can connect two x16 cypress SRAMs to the 32-bit bus of the controller.

 

In this case, in the read cycle, if the err signal from two SRAMs is set to be valid, the data in the SRAM device must be cleared and rewritten to maintain data integrity. Figure 7 shows the interface method in this case. Two 1mx16 (16 MB) SRAMs are connected in width expansion mode to create 1mx32 (32MB) storage space.

 

Interface between 65nm SRAM of cypress and ASIC / FPGA / controller

Figure 1 cypress SRAM interface

 

1.3 deep expansion

In some memory intensive applications, the available density of SRAM may not meet the memory requirements of applications. In this case, system designers can use cypress’s 65nm SRAM for deep expansion.

 

SRAM can be selected using a higher-order address signal (A20 in this example), while the remaining address signals from the two SRAMs, I / O signal, control signal and err signal, can be connected, as shown in Figure 8. Two 1mx16 (16 MB) SRAMs are connected in deep expansion mode to create 2mx16 (32MB) storage space. According to A20 signal, one SRAM device is enabled and the other is disabled. The disabled SRAM device will keep its err pin in Hi-Z state so that the active SRAM can drive the combined err signal correctly

 

 Interface between 65nm SRAM of cypress and ASIC / FPGA / controller

Figure 2 width expansion and err