FPGA / IC position — Summary of common questions in written interview of large companies


FPGA / IC position — Summary of common questions in written interview of large companies
1: What are synchronous logic and asynchronous logic?
Synchronization logic is that there is a fixed causal relationship between clocks. Asynchronous logic is that there is no fixed causal relationship between clocks. The answer should be consistent with the above question

(Supplement): features of synchronous sequential logic circuit: the clock ends of each trigger are all connected together and connected to the clock end of the system. The state of the circuit can be changed only when the clock pulse arrives. The changed state will be maintained until the arrival of the next clock pulse. At this time, each state in the state table is stable whether the external input x changes or not.

Characteristics of asynchronous sequential logic circuit: in addition to the trigger with clock, the trigger without clock and delay element can also be used as storage elements. There is no unified clock in the circuit, and the change of circuit state is directly caused by the change of external input.

2: Difference between synchronous circuit and asynchronous circuit:
Synchronization circuit: the clock inputs of all flip flops in the storage circuit are connected to the same clock pulse source, so the state changes of all flip flops are synchronized with the added clock pulse signal.

Asynchronous circuit: there is no unified clock in the circuit. The clock input of some flip flops is connected with the clock pulse source. The state changes of these flip flops are synchronized with the clock pulse, while the state changes of other flip flops are not synchronized with the clock pulse.

3: Essence of timing design:
The difficulty of circuit design is timing design. The essence of timing design is to meet the requirements of establishment / holding time of each trigger.

4: Establish the concept of time and hold time?
Setup time: the time when the data at the data input of the trigger must remain unchanged before the rising edge of the clock. Hold time: the time when the data at the data input of the trigger must remain unchanged after the rising edge of the clock.

Regardless of the skew of the clock, the establishment time of D2 cannot be greater than (the latest arrival time of data in clock cycle t-d1 tlmax + T2max); The holding time shall not be greater than (the fastest arrival time of D1 data t1min + t2min); Otherwise, the data of D2 will enter metastable state and propagate to the backward stage circuit

5: Why should triggers meet the setup time and hold time?
Because it takes a certain time to form the internal data of the trigger. If the establishment and holding time are not met, the trigger will enter metastable state. After entering metastable state, the output of the trigger will be unstable and change between 0 and 1. At this time, it needs a recovery time to stabilize its output, but the stable value is not necessarily your input value. This is why two-stage flip flops are used to synchronize asynchronous input signals. This can prevent the metastable state generated by the current level trigger from propagating to the following logic because the asynchronous input signal may not meet the establishment and holding time for the current level clock, resulting in the propagation of metastable state.

(easier to understand) another way to understand: the establishment time is required because segment D of the trigger is like a latch receiving data. In order to stably set the state of the front gate, it needs a period of stability time; Holding time is required because after the arrival of the clock edge, the trigger needs to feedback the stored state, and it takes time to transfer from the rear gate to the front gate.

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6: What is metastable? Why can two-stage flip flops prevent metastable propagation?
This is also a problem of asynchronous circuit synchronization. For details, please refer to edacn Technology Monthly 20050401.

Metastable state means that the trigger cannot reach an identifiable state within a specified time period. The circuit that uses two-stage trigger to synchronize asynchronous circuit is actually called “one-step peer”, which can only be used to synchronize one bit asynchronous signal. The principle that two-stage trigger can prevent metastable propagation: assuming that the input of the first stage trigger does not meet its establishment and holding time, its output data is metastable after the arrival of the first pulse edge, then its output metastable data must be stable after a recovery time before the arrival of the next pulse edge, Moreover, the stable data must meet the establishment time of the second stage trigger. If they are met, the second stage trigger will not be metastable when the next pulse comes, because the data at its input meets its establishment and holding time. Effective conditions of synchronizer: recovery time after the first stage trigger enters metastable state + establishment time of the second stage trigger < = clock cycle.

More specifically, the input pulse width must be greater than the sum of the synchronization clock cycle and the holding time required by the first stage trigger. The safest pulse width is twice the synchronous clock cycle. Therefore, such a synchronous circuit is more effective for asynchronous signals from a slower clock domain to enter a faster clock domain, but has no effect on entering a slower clock domain.

7: Maximum speed calculation (fastest clock frequency) and pipeline design idea of the system:
The speed of the synchronization circuit refers to the speed of the synchronization system clock. The faster the synchronization clock, the shorter the time interval for the circuit to process data, and the greater the amount of data processed by the circuit in unit time.


TCO is the delay time from the time when the input data of the trigger is input into the trigger by the clock to the time when the data reaches the output end of the trigger;

Tdelay is the delay of combinational logic;

Tsetup is the setup time of the D trigger.

Assuming that the data has been input into the D flip-flop by the clock, the delay time required for the data to reach the Q output of the first flip-flop is TCO, and the delay time after combinatorial logic is tdelay, and then reach the d end of the second flip-flop. It is hoped that the clock can be stably input into the flip-flop again in the second flip-flop,

The delay of the clock must be greater than TCO + tdelay + tsetup,

That is, the minimum clock cycle Tmin = TCO + tdelay + tsetup,

That is, the fastest clock frequency Fmax = 1 / Tmin.

FPGA development software also calculates the maximum running speed Fmax of the system through this method.

Because TCO and tsetup are determined by the specific device technology, the delay time tdelay of combinational logic can only be changed when designing the circuit. Therefore, shortening the delay time of combinational logic between triggers is the key to improve the speed of synchronous circuit.

Because the general synchronization circuit is larger than the first level latch, in order to make the circuit work stably, the clock cycle must meet the maximum delay requirements. Therefore, only by shortening the longest delay path can the working frequency of the circuit be improved.

The larger combinational logic can be decomposed into smaller n blocks, the combinational logic can be evenly distributed through appropriate methods, and then the trigger is inserted in the middle, and the same clock as the original trigger can avoid excessive delay between the two triggers and eliminate the speed bottleneck, so as to improve the working frequency of the circuit.

This is the basic design idea of the so-called “pipeline” technology, that is, the speed limited part of the original design is realized with one clock cycle. After inserting the trigger with pipeline technology, it can be realized with N clock cycles. Therefore, the working speed of the system can be accelerated and the throughput can be increased. Note that the pipeline design will add delay to the original data path, and the hardware area will be slightly increased.

8: Concept and basic strategy of timing constraints?
Timing constraints mainly include period constraints, offset constraints and static timing path constraints.

By adding timing constraints, the mapping and layout of generic cabling tools can be adjusted, so that the design meets the timing requirements.

The general strategy of attaching temporal constraints is to attach global constraints first, and then attach special constraints to fast and slow exception paths.

When adding global constraints, first define all the designed clocks, group the synchronization elements in each clock domain, add cycle constraints to the packets, and then add offset constraints to FPGA / CPLD input / output pad and padtopad path constraints of full combinational logic.

When special constraints are added, the paths between packets are constrained first, and then fast, slow exception paths, multi cycle paths, and other special paths are constrained.

9: The role of additional constraints?

1: Improve the working frequency of the design (reduce logic and wiring delay);

2: Obtain correct timing analysis report;

(the static timing analysis tool takes constraints as the standard to judge whether the timing meets the design requirements, so the designer is required to correctly input constraints so that the static timing analysis tool can correctly output timing reports)

3: Specify the electrical standard and pin location of FPGA / CPLD.

10: Direction of FPGA design engineers:
SOPC, high-speed serial I / 0, low power consumption, reliability, testability and optimization of design verification process.

With the improvement of chip technology, chip capacity and integration are increasing. FPGA design is also developing towards high speed, high integration, low power consumption, high reliability, high testability and verifiability.

Testability and verifiability of chips are becoming a necessary condition for complex design. Try to find bugs before board and advance the time of finding bugs, which is also the reason why some companies make great efforts to design simulation platforms.

In addition, with the improvement of single board function and the pressure of cost, low power consumption has gradually entered the consideration range of FPGA designers. When completing the same function, they consider how to minimize the power consumption of the chip. It is said that Altera and Xilinx are sorting out documents on how to reduce power consumption according to their own chip characteristics. The application of high-speed serial I0 also enriches the application range of FPGA, such as the high-speed link in Xilinx’s v2pro. In short, there is no end to learning. After mastering certain concepts and methods, we should start to consider other aspects of FPGA.

11: How to synchronize multi bit asynchronous signals?
For asynchronous signals with one bit, the “one bit synchronizer can be used for synchronization”, while for asynchronous signals with multiple bits, the following methods can be adopted:

1: The method of holding register and handshake signal (multi data, control, address) can be adopted;

2: Special application circuit structure varies according to different applications;

3: Asynchronous FIFO( The most commonly used cache unit is DPRAM)

12: What is the difference between FPGA and CPLD?
FPGA is a programmable ASIC.

ASIC: application specific integrated circuit, which is a special-purpose circuit designed and manufactured for a user.

According to the specific requirements of a user, it can supply fully customized and semi customized integrated circuits with low development cost, short delivery cycle. Compared with other ASIC, they have the advantages of short development cycle and no need for on-line inspection of ASIC.

13: What is the difference between a latch and a flip-flop?

Level sensitive memory devices are called latches.

It can be divided into high-level latch and low-level latch for signal synchronization between different clocks.

Bistable memory elements with cross coupled gates are called flip flops.

It is divided into rising edge trigger and falling edge trigger. It can be considered that two different level sensitive latches are connected in series.

The former latch determines the setup time of the trigger, and the latter latch determines the hold time.

14: What are the two kinds of memory resources in the FPGA chip?
There are two kinds of memory resources in FPGA chip:

One is called block ram, and the other is the internal memory configured by LUT (that is, distributed RAM).

Block ram is composed of a certain number of fixed size storage blocks. Using blockram resources does not occupy additional logical resources and is fast. However, when used, the blockram resource consumed is an integer multiple of its block size.

15: What is clock jitter?
Clock jitter refers to a temporary change in the clock cycle at a given point of the chip,

That is, the clock cycle may be lengthened or shortened in different cycles. It is an average variable with an average value of 0.

16: Use of clock in FPGA design( (e.g. frequency division, etc.)
A: FPGA chip has fixed clock routes, which can reduce clock jitter and deviation.

When the clock needs to be phase shifted or frequency converted, it is generally not allowed to carry out logical operation on the clock, which will not only increase the deviation and jitter of the clock, but also bring burrs to the clock.

The general processing method is to use the clock manager of FPGA chip, such as PLL, DLL or DCM, or convert the logic to the D input of trigger (these are also alternative schemes for clock logic operation).

17: How to realize the delay of synchronous sequential circuit in FPGA design?
First, let’s talk about the delay implementation of asynchronous circuit: half of asynchronous circuit is realized by adding buffer and two-stage NAND gate (I haven’t used it yet, so I’m not very clear), but this is not suitable for synchronous circuit to realize delay. In the synchronous circuit, for the relatively large and special delay, half of the counter is generated by the high-speed clock, and the delay is controlled by the counter; For relatively small delay, you can take a beat through the trigger, but this can only delay one clock cycle.

18: Three resources that can be integrated into RAM / ROM / CAM in FPGA and their precautions?
Three resources: block ram; Trigger (FF), lookup table (LUT);

Notes: 1: block ram resources should be preferred when generating ram and other storage units;

There are two reasons:

First, using block ram and other resources can save more FF, 4-LUT and other bottom programmable units. Using block RAM can be said to be “no use for nothing”, which is an embodiment of maximizing device efficiency and saving cost;

Second: block ram is a configurable hardware structure. Its reliability and speed are better than the memory built with LUT and register.

2: Clarify the hardware structure of FPGA and make rational use of block ram resources;

3: Analyze block ram capacity and use block ram resources efficiently;

4: Distributed RAM resource

19: Hardware primitives related to global clock resources and DLLs in Xilinx:
Common Xilinx device primitives related to global clock resources include:

Ibufg, ibufgds, bufg, bufgp, bufgce, bufgmux, bufgdll, DCM, etc. For the explanation of each device primitive, please refer to the P50 part of FPGA design guidelines.

20: The hierarchical concept of HDL language?
HDL language is hierarchical and typed. The most commonly used hierarchical concepts include system and standard level, function module level, behavior level, register transfer level and gate level.

21: principle and structure of lookup table?
The lookup table is called LUT for short. LUT is essentially a ram. At present, 4-input LUTS are mostly used in FPGA, so each LUT can be regarded as a 16×1 RAM with 4-bit address lines. When the user describes a logic circuit through schematic diagram or HDL language, PLD / FPGA development software will automatically calculate all possible results of the logic circuit and write the results into RAM in advance. In this way, each input of a signal for logic operation is equivalent to inputting an address, looking up the table, finding out the content corresponding to the address, and then outputting

22: IC Design front-end to back-end processes and EDA tools?
The front-end design is also called logical design, and the back-end design is also called physical design. There is no strict boundary between the two. Generally, the design related to process is the back-end design.

1: Specification formulation: the customer puts forward design requirements to the chip design company.

2: Detailed design: fabless comes up with design solutions and specific implementation architecture and divides module functions according to the specifications and requirements put forward by customers. At present, the verification of the architecture is generally based on SystemC language. The simulation tool of SystemC can be used for the simulation of the post consideration model. For example, cocentric and visual elite.

3: HDL coding: design input tools: ultra, visual VHDL, etc. 4: simulation verification: modelsim5: logic synthesis: synthesize

6: Static timing analysis: prime time of Synopsys

7: Formal verification: the formality of Synopsys

23: how to overcome and make use of parasitic effects in IC Design (this is my understanding. The original question seems to say how the feedback of parasitic effects in the IC design process affects the designer’s design scheme)?

24: design a 1-bit adder with FILP flop and logic gate, input carryin and current stage, and output

25: design an automatic beverage vending machine with 10 cents for drinks and 5 cents and 10 cents for coins, and consider the change,

Draw FSM (finite state machine)
When programming with Verilog, the syntax should meet the requirements of FPGA design
What tools can be used in design engineering and the general design process?

library IEEE;

use IEEE. STD_LOGIC_1164. ALL;



entitydrink_auto_sale is port(clk: in std_logic;

reset: instd_logic;

sw101: instd_logic;

sw102: instd_logic;

buy: out std_logic;

back: out std_logic);

enddrink auto_sale;

architecture Behavioral of drink auto sale is typestate_type is(st0, st1);

signalcs, ns: state_type; begin process(clk, reset)

begin if(reset=’1′)

then cS<=stO;

elsif(clk’ event and clk=’1′)

then cs<=ns;

end if;

Design process: set three states: 0 and 5; When the state is 0 minutes, it turns to 5 minutes after receiving the 5 minutes signal pulse;

When receiving the 10 minute signal pulse, turn to the 0 minute state and pop up the beverage without change;

When the status is 5 minutes, receive the 5-minute signal, pop up the beverage, do not change, and return to the 0-minute status;

When receiving the 10 point status, pop up the beverage, change and return to the zero point status.

Design tools used: ise7.1, Modelsim, synthesize

(I don’t know why the above state machine design can’t see the state machine flow chart in the RTL view of synthesize, so the state transition diagram is not drawn).

26: what is “line and” logic? What are the specific requirements for hardware characteristics to realize it?
Line and logic are two output signals connected to realize the function of and. In terms of hardware, OC gate should be used to realize it, because it is not used

The OC gate may cause excessive current and burn out the logic gate. At the same time, a pull-up resistor should be added to the output port. 0C gate is an open collector gate.

27: what is the phenomenon of competition and adventure? How to judge? How to eliminate?
In a combinational circuit, after an input variable is transmitted through different ways, the time to reach a convergence point in the circuit is first and then. This phenomenon is called competition;

The phenomenon of instantaneous error of circuit output due to competition is called adventure( That is, the burr caused by competition is called Adventure).

Judgment method: algebraic method (if there are opposite signals in Boolean formula, competition and adventure may occur);

Karnaugh Map: if there are two tangent Karnaugh circles and the tangent is not surrounded by other Karnaugh circles, competitive adventure may occur;

Experimental method: oscilloscope observation;


1: Add filter circuit to eliminate the influence of burr;

2: Add strobe signal to avoid burrs;

3: Add redundant items to eliminate logical risks.

28: do you know which logic levels are commonly used? Can TTL and COMS levels be directly interconnected?
Common logic level:


ECL(Emitter Coupled Logic)、

PECL(Pseudo/Positive Emitter Coupled Logic)、

LVDS(Low Voltage Differential Signaling)、

GTL(Gunning Transceiver Logic)、

BTL(Backplane Transceiver Logic)、

ETL(enhanced transceiver logic)、

GTLP(Gunning Transceiver Logic Plus);


There is also an answer: common logic level: 12V, 5V, 3.3V.

TTL and CMOS cannot be directly interconnected, because TTL is between 0.3-3.6v, while CMOS is between 12V and 5V. CMOS outputs connected to TTL can be directly interconnected. When TTL is connected to CMOS, a pull-up resistor shall be added at the output port to connect to 5V or 12V.

The high and low levels of CMOS are:



TT1: VIH > = 2.0V, VIL < = 0.8V; Voh>=2.4v,Vol<=0.4v.

TT1 can be directly driven by CMOS; TT1 can drive CMOS with pull resistance

1. When the TTL circuit drives the COMS circuit, if the high level output by the TTL circuit is lower than the lowest high level of the COMS circuit (generally 3.5V), then it is necessary to connect the pull-up resistor at the output end of the TTL to improve the value of the output high level.

2. 0C gate circuit must add pull resistance to improve the high-level value of output.

3. In order to increase the driving capacity of the output pin, pull-up resistors are often used on the pins of some MCU.

4. On COMS chip, in order to prevent damage caused by static electricity, unused pins cannot be suspended. Generally, pull-up resistance is connected to reduce input impedance and provide load relief path.

5. The pin of the chip is added with a pull resistance to improve the output level, so as to improve the noise tolerance of the chip input signal and enhance the anti-interference ability.

6. Improve the anti electromagnetic interference ability of the bus. When the pin is suspended, it is easier to accept external electromagnetic interference.

7. Resistance mismatch in long line transmission is easy to cause reflected wave interference. In addition, pull-down resistance is resistance matching, which can effectively suppress reflected wave interference.

The selection principles of pull-up resistance include:

1. It should be large enough to save power consumption and the current filling capacity of the chip; High resistance and low current.

2. It should be small enough to ensure sufficient driving current; Low resistance and high current.

3. For high-speed circuits, excessive pull-up resistance may flatten the edge. Considering the above three points, it is usually selected between 1K and 10K. There is a similar reason for the pull-down resistance.

The output level of the circuit must be increased by adding the resistance 0C.

When the 0C gate circuit needs to output “1”, it needs to add the pull resistance. Without it, there is no high level at all. Sometimes when we use the 0C gate as the driver (such as controlling an LED) to fill the current, we can not add the pull resistance. The 0C gate can realize the “line and” operation

0C gate is the open collector output

In short, the addition of pull resistance can improve the driving ability.

29: what is the difference between synchronous reset and asynchronous reset in IC design?
Synchronous reset takes reset signal along the clock to complete the reset action.

Asynchronous reset regardless of the clock, as long as the reset signal meets the conditions, the reset action is completed.

Asynchronous reset requires high reset signal without burr. If its relationship with the clock is uncertain, metastable state may also occur.

Features of the emore: 30 and the status of the emore?
The output of Moore state machine is only related to the current state value, and there will be state change only when the clock edge comes.

The output of Mealy state machine is related not only to the current state value, but also to the current input value.

31: how to process signals across time domain in multi time domain design?
The signal communication between different clock domains needs synchronous processing, which can prevent the metastable signal of the first stage trigger in the new clock domain from affecting the lower logic.

Signal synchronization across clock domain:

1. When a single signal crosses the clock domain, a two-stage trigger can be used for synchronization;

2. When the data or address bus crosses the clock domain, asynchronous FIFO can be used to realize clock synchronization;

3. The third method is to use handshake signal.

32: what are the advantages and disadvantages of static and dynamic timing simulation?
Static timing analysis uses the exhaustive analysis method to extract all timing paths existing in the whole circuit,

Calculate the propagation delay of the signal on these paths, and check whether the establishment and holding time of the signal meet the timing requirements,

By analyzing the maximum path delay and the minimum path delay, the errors violating the timing constraints are found.

It can exhaust all paths without input vector, and runs fast and occupies less memory. It can not only check the timing function of chip design, but also optimize the design by using the results of timing analysis. Therefore, static timing analysis has been more and more used in the verification of digital integrated circuit design.

Dynamic timing simulation is a common simulation, because it is impossible to produce a complete test vector covering every path in the gate level netlist. Therefore, in dynamic timing analysis, it is impossible to expose some possible timing problems on the path;

33: a four stage MUX, in which the second stage signal is the key signal. How to improve timing?
Key: put the second stage signal to the last output stage for output, and pay attention to modifying the chip selection signal to ensure that its priority has not been modified( Why?)

34: a gate level diagram is given, and the transmission delay of each gate is given. What is the critical path and the input is given, so that the output depends on the critical path?
35: why is the aspect ratio of P tube larger than that of N tube in a standard inverter?
Related to carriers, p-tube is hole conductive, n-tube is electron conductive, and the mobility of electrons is greater than holes. Under the same electric field, the current of n-tube is greater than that of p-tube. Therefore, it is necessary to increase the aspect ratio of p-tube and make it symmetrical, so as to make the rise time and fall time equal, the noise tolerance of high and low levels the same, and the charge and discharge time equal

36: build a two input NAND gate with MOS?
< fundamentals of digital electronic technology > page 49

37: draw the symbols of not, NAND and nor, the truth table, and the circuit of transformer level?

38: draw the CMOS diagram and draw the tow to one MUX gate?
39: XOR with one out of two MUX and one inv?
Among them, B is connected to the address input terminal, a and a are not connected to the data selection terminal, f corresponds to the output terminal, and the enable terminal is grounded and set to zero (not drawn)

40: draw the transistor level circuit diagram of CMOS circuit to realize y = a * B + C (D + e). (Shilan Microelectronics)?
41: using NAND gate to design full adder( Huawei)

42: A, B, C, D, e vote, the majority obeys the minority, and the output is f
(that is, if the number of 1 in a, B, C, D and E is more than 0, then f output is 1, otherwise f is 0),
With NAND gate implementation, there is no limit to the number of inputs?

43: draw the circuit diagram and layout of a CMOS D latch?

44: what are the concepts and differences between latch and DFF?
45:1atch is different from register. Why register is used now. How does the latch in the behavior level description come into being?
1atch is a level trigger and register is an edge trigger. Register acts under the edge trigger of the same clock, which is in line with the design idea of synchronous circuit, while latch belongs to asynchronous circuit design, which often leads to difficulties in timing analysis, and improper application of latch will waste a lot of chip resources.

46: use D flip-flop as a frequency division circuit? Draw the logic circuit?
This method is generally not used in display engineering design, and the frequency division is generally realized by DCM. The frequency division signal obtained by DCM has no phase difference.

47: what is a state diagram?
State diagram describes the state transition law of sequential logic circuit and the relationship between output and input in the form of geometry.

48: use your familiar design method to design a 7-ARY cycle counter with preset initial value. What about 15-ary?

49: what are the programmable logic devices you know?

50: write a piece of code in Verilog or VHDL to eliminate a glitch?

The burr can be eliminated by passing the transmitted signal through two-stage trigger( This is my own method: this method needs to meet certain conditions to eliminate burrs, but it can not be guaranteed to be eliminated.)

51: what are the differences between SRAM, false memory, and DRAM?

SRAM: static random access memory with fast access speed but small capacity. Data will be lost after power failure. Unlike DRAM, which requires constant refresh and has high manufacturing cost, it is usually used as cache memory

Flash: flash memory, with slow access speed and large capacity, will not lose data after power failure

DRAM: dynamic random access memory (DRAM) must constantly re strengthen the potential difference, otherwise the potential difference will be reduced to the point where there is not enough energy to show the state of each memory unit. The price is cheaper than SRAM, but the access speed is slow and the power consumption is large. It is often used as computer memory.

52: there are four multiplexing modes, frequency division multiplexing. Write the other three?
Four multiplexing modes: frequency division multiplexing (FDMA), time division multiplexing (TDMA), code division multiplexing (CDMA), wavelength division multiplexing (WDM)

53: when will setup time violation and hold time violation be revised in the ASIC design process? How to correct?
See setup time and hold time above

54: give a combinational logic circuit and analyze the logic function.
The so-called analysis of combinational logic circuit is to find out the relationship between the output and input of a given logic circuit, and point out the logic function of the circuit.

The analysis process is generally carried out according to the following steps:

1: According to the given logic circuit, the logic function expression of the output end is derived step by step from the input end.

2: List the truth table according to the output function expression;

3: Summarize the logic function of the circuit in words;

55: how to prevent metastable state?
1 reduce the system clock frequency 2 use faster FF

3. Introduce synchronization mechanism to prevent metastable propagation (the above-mentioned plus two-stage trigger can be used).

4 improve the clock quality and use the clock signal with fast edge change

56: contents of Kirchhoff theorem
Kirchhoff’s law includes current law and voltage law:

Current law: in a lumped circuit, the algebraic sum of branch currents of all outgoing nodes is equal to zero for any node at any time.

Voltage law: in a lumped circuit, at any time, along any circuit, the algebraic sum of all branch voltages is equal to zero.

57: describe the concept of feedback circuits and list their applications.
Feedback is to input the electricity in the output circuit into the input circuit in the circuit system.

The types of feedback are: voltage series negative feedback, current series negative feedback, voltage parallel negative feedback and current parallel negative feedback.

Advantages of negative feedback: reduce the gain sensitivity of the amplifier, change the input resistance and output resistance, improve the linear and nonlinear distortion of the amplifier, effectively expand the passband of the amplifier and adjust automatically.

Characteristics of negative voltage feedback: the output voltage of the circuit tends to remain constant. Characteristics of current negative feedback: the output current of the circuit tends to remain constant.

58: difference between active filter and passive filter
Passive filter: this circuit is mainly composed of passive components R, l and C

Active filter: it is composed of integrated operational amplifier and R and C. It has the advantages of no inductance, small volume and light weight.

The open-loop voltage gain and input impedance of the integrated operational amplifier are very high, and the output resistance is small. After forming the active filter circuit, it also has a certain role of voltage amplification and buffer. However, the bandwidth of the integrated operational amplifier is limited, so the working frequency of the current active filter circuit is difficult to be very high.

59: what is OTP and mask? What is the difference between them?
0tp means one time program, MTP means multi time program, one time program 0tp (one time program) is a memory type of MCU. MCU can be divided into mask ROM, OTP ROM, flashrom and other types according to its memory type.

The MCU of maskROM is cheap, but the program has been solidified at the factory, which is suitable for applications where the program is fixed; The MCU program of false hrom can be rewritten repeatedly, with strong flexibility, but the price is high, which is suitable for price insensitive applications or development purposes; The MCU price of OTPROM is between the first two. At the same time, it has one-time programmable ability. It is suitable for applications requiring both flexibility and low cost, especially electronic products with constantly renovated functions and requiring rapid mass production.

60. The single chip microcomputer does not operate after it is powered on. What should be checked first?
1) First, confirm whether the power supply voltage is normal. Use a voltmeter to measure the voltage between the grounding pin and the power pin to see if it is the power voltage, such as 5V.

2) The next step is to check whether the voltage of the reset pin is normal. Measure the voltage value of pressing the reset button and releasing the reset button respectively to see if it is correct.

3) Then check whether the crystal oscillator vibrates. Generally, use an oscilloscope to see the waveform of the crystal oscillator pin. Note that the “X10” file of the oscilloscope probe should be used. Another method is to measure the level of I0 port in the reset state, press and hold the reset key, and then measure the voltage of I0 port (except for Po port not connected to external pull-up) to see whether it is high level. If it is not high level, it is mostly because the crystal oscillator does not start vibration.

4) In addition, it should be noted that if the on-chip ROM is used (in most cases, it is rarely used for external ROM expansion), the EA pin must be pulled up, otherwise the program will run disorderly. Sometimes you can use an emulator, but you can’t burn the chip. It’s often because the EA pin is not pulled high (of course, there’s only one reason why the crystal oscillator doesn’t start). After the inspection of the above points, the fault can be generally eliminated.

5) If the system is unstable, it is sometimes caused by poor power filtering. Connecting a 0.luf capacitor between the power pin and the ground pin of the single chip microcomputer will be improved. If the power supply does not have a filter capacitor, it needs to be connected with a larger filter capacitor, such as 220uF. When the system is unstable, you can connect the capacitor (the closer you are to the chip, the better).

61: given the setup and hold time of reg, find the delay range of intermediate combinational logic

62: the clock cycle is t, and the maximum register to output time of trigger D1 is t1max and the minimum is t1min.
The maximum delay of combinational logic circuit is T2max and the minimum is t2min. Ask, what conditions should be met for the establishment time T3 and holding time of trigger D2


63: build an edge trigger with transmission gate and reverser( Yangzhi electronic written test)

64: draw D trigger with logic( Via Shanghai written test questions)

How many flip flops are needed in the 65:16 frequency division circuit?

66: what is the difference between blocking assignment and non blocking assignment?

Non blocking assignment: the assignment statements in the block are assigned at the same time, which is generally used in the description of sequential circuits.

Blocking assignment: the operation of the next sentence can only be performed after the assignment statement is completed. It is generally used in combinatorial logic description.

67: the sequence detection module of 101101 is implemented with FSM.
(bridge of Nanshan) a is the input and B is the output. If the continuous input of a is 1101, the output of B is 1, otherwise it is 0.

For example, a: 0001100110110100110


Please draw state machine; Please use RTL to describe its state machine( (unknown)

library IEEE;




.ALL;entitydetect stream isport(clk:in std_logic;reset:in std_logic;data:in std_logic;result:out std_logic);

68: write a FIFO controller with Verilog / vhd1 (including empty, full and half full signals).
(Philips Datang written test) reg [n-1:0] memory [0: M-1];

FIFO is defined as eight always modules with n-bit word length capacity M. two are used to read and write FIFO, two are used to generate header address head and tail address, one generates counter count, and the remaining three generate empty, full and half full signals according to the counter value to generate empty, full and half full signals.

69: an existing user needs an integrated circuit product,
The product is required to realize the following functions: y = 1nx, where x is a 4-bit binary integer input signal. Y is binary decimal output,

Two decimal places are required. The power supply voltage is 3 ~ 5V. Assuming that the company receives the project,

We are responsible for the design of the product,

Try to discuss the whole design process of the product( Shilan Microelectronics)

70: similarities and differences between IIR and FIR filters
Clock tree synthesis is a step in ASIC design,

Its purpose is to make the clock drive all triggers at the same time as much as possible, which is the so-called synchronization circuit,

The same time here requires the same phase from the clock to all flip flops, because some flip flops are far from the CLK source and need many cycles to arrive.

There is a problem here. If you only rely on the connection, you can’t guarantee that the phase of the clock reaching the trigger is the same,

So you can add a buffer, which is an even number of inverters. It can shorten the delay, so you can adjust the delay through the number and type of added buffers to make the clock reach the same phase of the trigger, so as to realize the synchronization function. Of course, another function of inserting a buffer is to increase the driving capacity, If not, the clock source alone cannot drive so many triggers.

When it comes to FPGA, FPGA is composed of many logic units, including gates, look-up tables and triggers, that is, its triggers have been completed, that is, before leaving the factory, the connections between the internal components of FPGA have been completely fixed, and our programming only selects which are connected and which are disconnected on this basis.

FPGA cannot dynamically insert the buffer to achieve the same phase of the clock reaching the trigger.

In other words, the clock tree structure has been arranged in advance. What we can do is to use various resources to process the clock on this basis, such as frequency division, frequency doubling and gated clock. Therefore, FPGA can not talk about clock tree, but clock management.

Summary of common interview basic questions
1 Digital IC (ASIC) design process:

IC design is divided into front-end and back-end. The front-end design mainly uses HDL language — > netlist, and the back-end design is netlist — > chip layout.

The front end mainly includes requirements analysis and architecture design, RTL design, simulation verification, logic synthesis, sta and formal verification. The back end mainly includes DFT, layout planning, cabling and layout physical verification.

2 MCU structure:

It is composed of CPU system, program memory (ROM), data memory (RAM), various I / O ports and basic functional units (timer / counter, etc.).

3. Low power technology:

The power consumption can be described by the formula: power = kfcv ^ 2, that is, the power is equal to the constant coefficientworking frequency Load capacitance * square of voltage.

Therefore, the power consumption can be reduced from the following aspects:

a. Control the working frequency: reduce the frequency, increase the data path width, adjust the dynamic frequency, and gate the clock (the clock enters the register clock input pin only when the clock is enabled)

b. Reduce capacitive load: using logic gates with smaller geometric size, the capacitive load is small and the power is reduced.

c. Reduce the working voltage: dynamically change the working voltage and zero operating voltage (directly turn off part of the power supply in the system).

4. Basic concept and drawing of MOS tube:

MOS in Chinese means metal oxide semiconductor field effect transistor, which is composed of gate (g), drain stage (d) and source stage (s). It is divided into PMOS and NMOS. The difference is that at g-level high level, n-tube is on and p-tube is off. The two often appear in pairs, namely CMOS. As long as one is on, the other is not on. Modern single chip microcomputer is mainly made of CMOS technology.

Drawing generally needs to draw the CMOS circuit diagram structure according to a simple logical expression. You need to master the implementation of common logic gates.

Generally speaking, it’s good to remember that NAND gate and NOR gate are two MOS transistors at the top and bottom, PMOS at the top and NMOS at the bottom. The difference is that and non are “parallel up and down” or “parallel up and down”.

5. Internal structure and resources of FPGA:

FPGA is mainly composed of programmable unit, programmable I / O unit and wiring resources.

Programmable logic unit (configurable logic unit, CLB) is composed of two slices. Slice mainly includes LUT to realize combinatorial logic and trigger to realize sequential logic. The FPGA also includes special storage unit Bram, operation unit DSP slice, and special embedded functional units, such as PLL, SerDes, etc.

6. Principle of realizing combinational logic by LUT in FPGA:

LUT is equivalent to ram storing truth table corresponding to logical expression. The software lists all possible results of the logical expression and stores them in RAM, inputs them as RAM address and outputs them as logical operation results. If LUT is used to simulate two input and logic. List the truth table: 00 — 0, 01 — 0, 10 — 0, 11 — 1. At this time, take 00 01 10 11 as the address line and store the result 0 01 in RAM in turn. When input 00 and output 0 & 0 = 0

7 common logic expression simplification formula:

The left-right relationship isChange +, + change

Commutative law: aB = BA         A+B = B+A

Law of association: (a)B)C = A(BC)      (A+B)+C = A+(B+C)

Distribution rate: a (B + C) = AB + AC, a + BC = (a + b) (a + C)

Special laws:

8 function expression, characteristics and structure of FIR filter and IIR filter:

Fir (finite impulse response) filter: non recursive, with linear phase. IIR (infinite impulse response) filter: recursive structure, nonlinear phase. With the same order FIR and IIR filters, IIR filter has better filtering effect, but it will produce phase distortion.

FIR filter:

N sampling data are weighted and averaged.


Structure diagram:

IIR filter:

Contains both recursive and non recursive parts.

Expression: (with n feedforward coefficients and M-1 feedback coefficients)

Structure diagram:

9. For the data range represented by n-bit binary numbers, how many bits are required after the addition and multiplication of two nbit numbers( More indirect questions in calculation questions)

Signed number: (complement) – 2 ^ (n-1) ~ 2 ^ (n-1) – 1 if n = 8, the range is: – 128 ~ 127

Unsigned number: 0 ~ 2 ^ n-1. If n = 8, the range is 0 ~ 255

Number of fixed points: 3q13 range: – 4 ~ 4-2 ^ (- 13) accuracy: 2 ^ (- 13)

The data bit width required after addition and multiplication. If there is no known data range, follow the basic law: addition bit width + 1, multiplication bit width * 2. If the operand range is known, calculate the limit value of the operation result according to the maximum absolute value of the number that can be represented by the operation operand.

Q: for example, when two 8bit signed numbers are multiplied, what is the bit width required for the result?

A: the data range represented by the 8-bit signed number complement is: – 128 to 127, and the number with the maximum absolute value is – 128, so in the limit case, it is – 128 * (- 128) = 16384 = 2 ^ 14. The range represented by the 15 bit signed number complement is: – 2 ^ 14 to 2 ^ 14-1, which cannot represent 2 ^ 14. To sum up, 16 bit width is required. Just double the bit width.

10 FPGA detailed design process (interview questions)

Similar to the digital IC design process, taking Xilinx vivado tool as an example, it mainly includes the following steps: system planning, RTL input, behavior simulation, logic synthesis, post synthesis simulation (optional), post synthesis design analysis (timing and resources), design implementation (including layout, wiring and Optimization), post implementation design analysis (timing and resources), board level debugging and bitstream solidification.

11 timing constraint correlation

What are the timing paths:

Input paths: external pin to internal module path

Register to register paths: system internal register to register paths

Output paths: the path from the internal module to the external pin

Port to port paths: path from FPGA input port to output port (not commonly used)

Key steps to create timing constraints:

A baseline constraint: create clocks define clocks interactions B I / O constraint: set input and output delays C exception constraint: set timing exceptions (set)_ max_ delay/set_ min_ delay、set_ multicycle_ path、set_ false_ path)

At the initial stage of design, I / O constraints may not be added, but baseline constraints should be established as soon as possible.

Input delay and output delay calculations:

input delay:

A system synchronization: Min_ delay  Tco min + Trce min

        max_delay      Tco max + Trce max

Bsource synchronization:   min_ delay     Tco min

        max_delay    Tco max

output delay:

min_delay  Trce min – Th

max_delay    Trce max + Tsu

In the source synchronization mode of input delay, DDR sampling mostly adopts oscilloscope to measure delay.

Relationship between Tsu and th and TCO t Tdata:



12 asynchronous signal synchronization mode

Single bit data, detect the signal change edge after two beats. If the fast clock domain signal enters the slow clock domain, expand the bit width first and then make two beats.

Multi bit data, using asynchronous FIFO bridging. When the amount of data is small and the bandwidth requirement is not high, the handshake synchronization mode can be adopted (the two beat synchronization mode of single bit handshake signal can be used to find the data stability time to ensure that the data is stable when the upstream handshake signal is raised).

13 difference between SRAM and DRAM

SRAM is a static random access memory, which stores data by transistors without refresh and has fast reading and writing speed. DRAM is a dynamic random access memory, which stores data by capacitors. Due to capacitor leakage, it needs to be refreshed dynamically, and the reading and writing speed of capacitors is lower than that of SRAM. However, DRAM has low cost and is suitable for high-capacity off chip cache.

How to identify and eliminate the concepts of competition and adventure in logic design?

Competition: in the combinational logic circuit, the signal reaches the output through multiple paths. The logic gates passed by each path have different time difference, and there is sequence at the moment of signal change. This phenomenon is called competition.

Adventure: the phenomenon that unexpected signals appear in the circuit output signal due to competition, resulting in instantaneous errors is called adventure. It shows that there is a narrow pulse at the output end, that is, burr, which is not in the original design.

The common logic algebra method judges whether there is competitive risk: as long as the output logic expression contains the “and” or “relationship between the original variable a and the inverse variable / a of a signal, and a and / a pass through different propagation paths, there is competition. The first solution is to modify the logic expression to avoid the above situation. The second is the sampling timing logic, which samples only at the edge of the clock, and eliminates the narrow pulse by paralleling the capacitor outside the chip.

Characteristics and application of 15 gray code

There is only single bit signal change between continuous gray codes, which is mostly used in asynchronous clock domain processing. For example, the index of address pointer in asynchronous FIFO adopts gray code coding.

Analysis: when only a single bit signal crosses the clock domain, we can get effective pulses in another clock domain through the synchronizer composed of double flip flops. However, if the same method is adopted for multi bit signals, the update time of each bit will be inconsistent, resulting in data error. In the asynchronous FIFO design, the signals on both sides belong to different clock domains. FIFO must give the empty and full indication signal by comparing the read-write address pointer values from different clock domains. The address pointer needs multiple bit signals to represent the FIFO depth. The single bit variation of gray code is just suitable for this occasion. The single bit signal synchronization strategy is completely suitable for Gray code.

Causes and elimination methods of metastable state

In asynchronous system, the register establishment and holding time is not satisfied, resulting in metastable state. Typical occasions are data transmission across clock domain and asynchronous reset circuit. In the process of asynchronous transmission, metastability is eliminated by single bit signal, double register synchronization and multi bit signal FIFO bridging (in fact, asynchronous signal synchronization is the elimination of metastability in the process of asynchronous transmission). Through asynchronous reset, synchronous release can eliminate the metastable state caused by asynchronous reset.

How to use C language to write sub functions with multiple return values

There are two common ways: one is to use global variables. When a sub function modifies multiple global variables during execution, it can achieve the same effect as multiple return values. Second, the array pointer is used as the function parameter to change multiple arguments themselves through address transfer.

18. The concept and causes of clock jitter and clock offset, and how to avoid them?

Clock jitter: refers to the uncertainty of the jump edge of the clock signal, so it is inconsistent in the clock frequency.

Clock offset skew: refers to the different time points when each sub clock signal generated by the global clock reaches different triggers, which is the inconsistency of clock phase.

Jitter is mainly caused by external interference, which can be avoided by various anti-interference means. The skew is caused by the different layout, wiring length and load of each path in the digital circuit. It can be eliminated by using the global clock network.

What is the difference between CMOS and TTL circuits?

The differences between the two are mainly reflected in three aspects:

a. Structure: CMOS circuit is composed of FET and TTL is composed of bipolar transistor.

b. Level range: CMOS logic level range is large (5 ~ 15V), and TTL only works below 5V. Therefore, CMOS noise tolerance is larger than TTL and has strong anti-interference ability.

c. Power consumption and rate: the power consumption of CMOS is smaller than TTL, but the operating frequency is lower than TTL.

What is the significance of 20 signal 3dB bandwidth?

3dB bandwidth usually refers to the frequency range defined when the highest point of power spectral density drops to 1 / 2.

21 JTAG interface signal and function

JTAG actually uses only four signals: clock TCK, state machine control signal TMS, data input signal TDI and data output signal TDO.

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