FPGA configuration using high speed SPI NOR Flash


NOR flash memory is widely used as FPGA configuration device. The application of FPGA in industrial, communication and automotive ADAS applications depends on the low latency and high data throughput characteristics of NOR flash. A good example of fast start-up time requirements is the camera system in the automotive environment. The speed shown on the instrument panel in the rear view at ignition is a first-order design challenge.


After power on, the FPGA will immediately load the configuration bit stream stored in nor device. After the transmission is completed, the FPGA is converted to the active (configured) state. FPGA includes many configuration interface options, usually including parallel nor bus and serial peripheral interface (SPI) bus. There is always a small incompatibility between the products provided by different manufacturers, which makes the multi-source procurement of storage devices more difficult.


History of FPGA configuration


Parallel EPROM was chosen as the configuration memory when FPGA was first introduced. NOR Flash technology has emerged and is widely used because of its in system reprogrammability and cost-effectiveness. The second evolution is that SPI memory interface has replaced parallel nor interface in most applications. Today’sSPI Nor FlashProducts offer high density and small packages, high read throughput, and (most importantly) efficient low pin number interfaces.


FPGA configuration using high speed SPI NOR Flash

Figure 1 – Gigabit four channel SPI (6-pin) and parallel nor (45 pin) interfaces


Figure 1 shows the pin arrangement of a 1 GB SPI device and a 1 GB parallel nor product. For a Gigabit memory, the four channel serial peripheral interface (QSPI) device has a six pin interface, while the parallel nor device requires 45 pins. The huge difference in the number of pins leads to the widespread use of QSPI devices as the preferred configuration interface. The QSPI interface allows you to change the density without changing the device size.


FPGA configuration speed


With the reduction of process nodes, FPGA devices continue to increase the number of programmable logic available. This results in higher density and faster configuration memory. Modern FPGA needs to load up to 128MB of data during configuration. These high-density configuration bit streams take longer to transfer from NOR flash device to FPGA. The configuration interface is not only optimized for read throughput, but also focused on promoting interoperability between different nor flash memory manufacturers.