FPGA based TDC Research Report

Time:2022-7-31

I amSnowy fish, an FPGA enthusiast, his research direction is FPGA Architecture Exploration and digital IC design.

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Recently, I investigated the implementation of TDC based on FPGA platform and wrote a research report.

FPGA based TDC Research Report

Now share some contents as follows:
Link to full report: https://download.csdn.net/download/qq_44447544/83046072

1、 Introduction to TDC

1.1 what is TDC?

Lidar system detects the contour, position, speed and other information of the target object by emitting laser beam. At present, the mainstream method of laser ranging system is time of flight measurement scheme, and the ranging information comes from the time interval value of incident signal and echo signal. The time measurement is completed by TDC (time to digital converters), which directly determines the parameter performance of the ranging system.

FPGA based TDC Research Report
<center> Figure 1 lidar ranging </center>

1.2 basic principles of TDC Technology

1.2.1 direct counting method

FPGA based TDC Research Report

<center> Figure 2 Schematic diagram of direct counting method </center>

Direct counting method is to count the complete number of clock cycles in the time interval by using the clock cycle of the system, so as to realize the measurement of the time interval. As shown in Figure 2, t~0~ is the measured time interval, t~1~ is the start time of the measured time interval, and t~2~ is the end time of the measured time interval, then the theoretical time interval t~0~=t~1~ – t~2~. However, since the clock signal is counted by an integer number of cycles, the start signal or end signal does not completely coincide with the rising edge of the clock signal in the actual measurement, so the final measurement result will bring an error of up to two clock cycles, that is, t~1~ +t~2~.

1.2.2 basic tap delay chain TDC

The basic tap delay chain TDC is composed of basic D flip flops and delay units. Using the delay characteristics of delay units, the states of these delay units are led out by tapping for time interval measurement.

FPGA based TDC Research Report

<center> Figure 3 Schematic diagram of basic tap delay chain construction </center>

Figure 3 is the structural schematic diagram of the basic tap delay chain. The start signal generates a certain delay after passing through the delay unit, connects the output end of the delay unit to the signal input end of the D trigger, and the stop end signal is used as the clock signal of the D trigger. During the measurement, when the rising edge of the stop end signal arrives, the D trigger will lock the status of all taps, and the time measurement is realized by calculating the number of start signals passing through the delay unit to determine its position.
As shown in Figure 4, when the stop signal arrives, the trigger Latch value of the start signal that has passed through the delay unit is 1, and the trigger Latch value that has not passed is 0, then the time interval between the start signal and the stop signal is the product of the number of D trigger outputs of 1 and the delay time of a single delay unit.

FPGA based TDC Research Report

<center> Figure 4 time interval analysis of start signal and stop signal </center>
The number of delay units that the start signal passes when the cut-off signal arrives, n_ TDC, and finally the time interval value is:

FPGA based TDC Research Report

Where t~buf~ is the delay time of a single delay unit. The resolution of the basic tap delay chain TDC is the delay time of a single delay unit in the delay chain, and the delay time of the delay unit should be the sum of the delay time of the delay element and its routing delay.

1.2.3 cyclic delay chain TDC

The above basic tap delay chain TDC will increase the nonlinearity of the TDC system due to the inconsistent delay time of the delay units in the delay chain, and the longer the length of the delay chain, the greater the nonlinearity, sometimes covering one or even several least significant bits (LSB), resulting in relatively large errors. If the time interval to be measured is large, the length of the delay chain needs to be increased, but the resources in FPGA are limited and sometimes can not meet its requirements, so it is necessary to design the delay chain as a ring structure. By reusing the same delay unit, we can not only reduce the impact of the delay time of the delay unit on the system linearity, but also save resources in FPGA.

FPGA based TDC Research Report

< center > Figure 5 TDC schematic diagram of cyclic delay chain method </center>
The cyclic delay chain TDC shown in Figure 5 is constructed by connecting the first and last signals of the delay chain through a data selector, and using a loop counter to count the number of cycles of the signal cycle. This design can ensure that the measurement range of TDC can be expanded without changing the number of delay units. In this TDC, when the rising edge of the stop signal arrives, the stop signal acts as a clock signal to latch the status of all triggers and terminate the cycle counter counting. The function of time interval measurement can be realized through the latch value of the loop counter and the trigger.

1.3 main technical indicators of TDC

(1) Resolution
Resolution refers to the minimum time interval that TDC can distinguish, which can also be called least significant bit (LSB). The smaller this parameter is, the better. It is the quantization step of TDC input-output transmission characteristic curve.
(2) Measuring range
The measurement range refers to the maximum time interval that TDC can measure. If you want to obtain a larger measurement range, it will generally occupy more area and logic resources of the chip.
(3) Nonlinearity
The nonlinear error of TDC refers to the deviation between the actual quantization characteristics and the ideal quantization characteristics of TDC caused by the inconsistent delay time of the delay unit, different chip manufacturing processes, changes in chip voltage and temperature, and signal crosstalk.
The analysis of TDC nonlinearity is mainly measured by differential nonlinearity (DNL) and integral nonlinearity (inl). Where DNL refers to the deviation between the delay time of the actual delay unit of TDC and the delay time (average value) of the ideal delay unit, which is the difference between the actual step size and the theoretical step size in the input-output transmission characteristic curve, while inl refers to the integral value of DNL from the starting position to the current position along the whole delay chain. DNL and inl are generally expressed in terms of the delay time of the ideal delay unit, that is, the time of an LSB.
(4) Measurement accuracy
Measurement accuracy, also known as single precision or standard deviation, refers to that when TDC measures the time interval of pulse signal, due to the influence of internal and external factors, the actual measured value is distributed around the real time value.
(5) Dead time
Dead time is the time that TDC completes the conversion and is ready to perform a new measurement. This index reflects the measurement rate that TDC can run. Modern applications require TDC to have a higher sampling rate, so the smaller the dead time, the better.
(6) Power consumption and resource occupation
In Digital IC, power consumption is mainly composed of static power consumption and dynamic power consumption. The former is determined by process, and the latter is determined by clock frequency and flip frequency. In addition, the logical resources occupied by TDC also need to be considered, and whether the allocation of system logical resources is reasonable to maximize energy efficiency.

Link to full report: https://download.csdn.net/download/qq_44447544/83046072

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