Embedded system: QE bit: a common factor that causes serial nor flash to download / start normally under i.mxrt

Time:2020-11-22

Hello, everyone. I’m a ruffian. I’m a real technical ruffian. What ruffian Heng introduced to you today isQE bit: a common factor that causes serial nor flash to download / start normally under i.mxrt

i. It has been more than two years since the launch of mxrt Series MCU, and more and more customer products based on i.mxrt have come into full bloom. As a system application engineer of i.mxrt product line, PI Ziheng could do reference design as much as possible in the early days, but now it is occupied by customer support for a large amount of time.

Because I. mxrt series does not have built-in flash (rt1064, In addition to sip models such as rt1024), it is the top priority of the customer project to configure a serial nor flash to start. There are many manufacturers of serial nor flash, and customers have a lot of choices. Therefore, we have to deal with the vast number of flash models together with customers. Ruffian Heng often ridicules himself as a flash test engineer.

In the process of supporting customers to solve the problem of downloading and starting serial nor flash, several common factors are encountered. These factors may affect the normal use of flash under i.mxrtSFDP factorsToday, ruffian Heng focuses on the QE bit factor.

1、 What is QE bit?

QE is the abbreviation of quad enable, which is called four line enable in Chinese. We need to explain this concept in combination with QSPI nor flash (ISSI is25wp064ajble) which is placed by default on i.mxrt evk.

1.1 definition of QE

The following is the pin diagram of is25wp064ajble, which is also the most classic QSPI nor flash package (soic-8). There are 8 pins. In addition to the necessary power and ground, there are 6 signal wires left. Pin1 / 2 / 5 / 6, which is surrounded by blue box, is a common SPI interface in embedded communication. In addition, there are two signal lines PIN3 / 7 enclosed in green frame. They are function multiplexed. To explain QE, it is related to their function positioning.

In other words, QE can be simply said that PIN3 / 7 is used as io2 / 3 as data transmission function, which is QE enabled, while PIN3 / 7 is used as WP ා and hold ා control functions, but QE is not enabled.

1.2 significance of QE

QE does not enable PIN3 / 7 to be used as WP ᦇ and hold ා, which is easy to understand. It is to protect flash data security through external pin level setting (mainly to avoid being erased by mistake). So what’s the point of QE enabling? This has to start with QSPI nor flash mode.

A standard nor flash operation sequence is normal, which is composed of four parts: CMD + addr + dummy + data. How to transmit these data determines the flash working mode. From the big classification, flash working mode can be divided into two modes: SPI mode and QPI mode

  • SPI mode: the data line IO0 is the big brother, and the CMD can only be sent by IO0. Other data transmission can be connected with IO [3:1] (how to do this? There are many ways, which will be introduced later)
  • QPI mode: four data lines IO [3:0] have equal status, and all data transmission is carried out by four brothers. In terms of I / O utilization efficiency, it is the highest.

Flash chips are powered on in SPI mode by default, so it needs to send a special command (qpien – 0x35) in SPI mode to enter QPI mode. Moreover, after entering QPI mode, QE control function will not be effective (no matter what QE setting is, it is equivalent to QE enabled state). The reason is that IO [3:0] must be on in QPI mode. Because i.mxrt bootrom does not support QPI mode by default (it is OK if you want to, but it is troublesome), so we only discuss SPI mode.

Flash operation is mainly read, write, erase, we will discuss SPI mode with the most common read. Continue to look at is25wp064ajble manual to find its command set. You can see that there are nine kinds of commands to read. If DTR (double edge sampling) is not included, there are 6 kinds of SDR (single edge sampling). As mentioned by ruffian Heng, there are many ways to transmit data in io [3:0] under SPI mode.

This paper focuses on normal read mode (Nord – 0x03) with the lowest efficiency and fast read Quad I / O (frqio – 0xeb) with the highest efficiency. The following figure is a time sequence comparison between the two. You can see that in Nord mode (on the left side of the figure below), only IO [1:0] is used to send commands and addresses, while IO1 is responsible for receiving data, and the highest SCK is 50MHz. In frqio mode (right side of the figure below), all addresses and data are completed by IO [3:0] except that IO0 sends commands, and SCK can reach 133MHz, which is comparable to QPI mode.

In order to make full use of flash to execute code (XIP), we certainly hope that flash can work in frqio mode, and the normal use of frqio mode obviously depends on QE settings.

2、 QE bit position difference

The QE function was introduced before. How to set QE function in flash? In fact, in addition to memory block, flash usually has some registers to record user configuration or save state.

2.1 several different QE bit designs

The following is the status register of is25wp064ajble, which has only one Sr, in which Sr1 [6] is QE bit, which is used to set QE function. It should be noted that QE bit is non-volatile, which means that the QE setting will still be in case of power failure of flash.

There is a special CMD for reading and writing SR in is25wp064ajble, in which the command word for writing Sr (wrsr) is a common 0x01:

Is the QE bit designed by all flash manufacturers according to the above method? I’m sorry, it’s not! Let’s take a look at a w25q64jvsim from Huabang. There are three SRS in it, and Sr2 [1] is QE bit

In w25q64jvsim, there are three groups of CMD for reading and writing Sr. among them, the command word for writing Sr2 to set QE is 0x31:

It seems that in QE bit design, flash of different manufacturers is not necessarily the same. As far as ruffian Heng knows, there are at least four different QE bit designs on the market at present, and ruffian Heng will not list them one by one. What’s more, the QE design of different series of flash from the same manufacturer may be different, such as Zhaoyi’s innovative flash.

2.2 SFDP – jesd216a specification

For different QE bit designs, it becomes a little difficult to open QE with a set of software drivers. What should we do? JEDEC came out. A ruffianSFDP factorsIt is mentioned in the first section of this paper that jesd216 standard has developed five versions since 2011. The original version of jesd216 does not define the QE bit position (the basic flash parameter table in SFDP only contains 9 dwords). Since jesd216a, QE bit location information has also been recorded in SFDP table (the basic flash parameter table is extended to 16 dwords), and QE bit location information is also recorded in the SFDP table Bit information is recorded in table 15 as follows:

Therefore, for flash that does not support SFDP or is only SFDP version jesd216, we need to manually check its data manual to find QE bit information. For flash of jesd216a and above, we can read SFDP table directly to know QE bit information.

3、 Default QE bit status

Now that we have a comprehensive understanding of QE bit, the last question remains. What is the initial state of QE bit of flash produced by various manufacturers? According to PI Ziheng’s understanding, almost all manufacturers have flash models with QE on or off by default. This is reflected in the part number. For example, the naming rules of Huabang w25q series are as follows. The last one represents the default QE status:

Other flash manufacturers have different naming rules for QE status, so you need to check the manual to understand.

4、 How to deal with flash with different QE bits in i.mxrt

Now we will start to explore the impact of different QE bit conditions on i.mxrt download and startup. The first step is to check whether flash has SFDP and identify its SFDP version.

4.1 define SFDP version

Take is25wp064ajble, which is the default on i.mxrt evk, as an example. From the data manual, it supports SFDP, but the specific jesd216 version cannot be found. Therefore, we need to read SFDP directly from flash, find the minor revision in the first parameter header, and find its value is 0x06, namely jesd216b.

enum
{
    kSfdp_Version_Major_1_0 = 1,
    kSfdp_Version_Minor_0  = 0, // JESD216
    kSfdp_Version_Minor_A  = 5, // JESD216A
    kSfdp_Version_Minor_B  = 6, // JESD216B
    kSfdp_Version_Minor_CD = 7, // JESD216C, JESD216D, JESD216D.01
};

4.2 set QE information to download

Because the SFDP version of is25wp064ajble is higher, its QE information can not be viewed from the manual. If flash does not support SFDP or SFDP is the first version, you need to check the data manual to record the QE bit position and initial status.

We know that both JLINK, IDE download algorithms and mpg mcuboot utility tools are basically the same set of download algorithm design under i.mxrtROM API implementation of IAPIn Section 2.2. For the classic four wire QSPI nor, we only need to modify the option value.

For is25wp064ajble under i.mxrt1060, we directly set option = 0xc0000008. In other words, the speed is 133MHz, and QE is notconfig by default (note that option [11:8] means quadmode). Why is notconfig set in QE? That’s because the SFDP version of this flash is high. The download algorithm can find QE information from SFDP and try to enable it.

enum
{
    kSerialNorQuadMode_NotConfig = 0,
    kSerialNorQuadMode_StatusReg1_Bit6 = 1,
    kSerialNorQuadMode_StatusReg2_Bit1 = 2,
    kSerialNorQuadMode_StatusReg2_Bit7 = 3,
    kSerialNorQuadMode_StatusReg2_Bit1_0x31 = 4,
};

If the flash is not SFDP or jesd216 and QE is off by default, then the option [11:8] must be set correctly, otherwise an error will be reported when downloading verification. For example, w25q64jvsim is not sure what SFDP version it is. To be on the safe side, we can directly set option = 0xc0000408.

The above option QE setting corresponds to the mcuboot utility download tool of PI Zi Heng

4.3 matching fdcb to start

When downloading, if QE in flash can be opened successfully, i.mxrt can start without doing anything special, and can directly use fdcb provided in SDK. In order to achieve the highest XIP performance, LUTS in fdcb are equipped with fast read in 4-wire I / O mode, and QE is turned on at this time, so there will be no problem for CPU to read instructions in flash.

So far, the QE bit ruffian scale, which causes the serial nor flash to fail to download / start normally under i.mxrt, has been introduced. Where is the applause~~~

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