DMA controller of STM32 network


The block diagram of STM32 network controller is as follows:


In the previous article, we have explained:

①External PHY Intereface:《STM32 network circuit design

② MAC controller:《Stm32mac controller

Next, we will explain part ③, DMA controller of STM32 network.

01. DMA controller operation

DMA has an autonomous transmit and receive engine and a CSR (control and status register) space. The transmitting engine transmits data from the system memory to the txfifo, while the receiving engine transmits data from the RX FIFO to the system memory.

The controller (i.e. DMA) uses descriptors to effectively move data from the source address to the destination with little CPU intervention. DMA is designed for packet oriented data transfer, such as frames in Ethernet.

The controller can be programmed to interrupt the CPU, such as when the frame sending and receiving transmission operations are completed and under other normal / error conditions.

DMA and stm32f20x   Stm32f21x and stm32f21x communicate through the following two data structures:

  1. Control and status register (CSR)

  2. Descriptor list and data buffer.

The DMA controller sends the received data frames to the reception cache of stm32f20x and the memory of stm32f21x. It can also send data frames from the transmission cache of the memory of stm32f20x, and the descriptor located in the memory of stm32f20x points to these caches.

There are two descriptor lists: one for receiving and one for sending.

The DMA descriptor is shown in the figure below. The ring structure is on the left and the chain structure is on the right.


02. DMA descriptor

Ethernet driver library stm32f2x7 provided by St_ The link structure used in eth. C is as follows:


Descriptor considerations:

1. An Ethernet packet can span one or more DMA descriptors

2. A DMA descriptor can only be used for one Ethernet packet

3. The last descriptor in the DMA descriptor list points to the first one to form a chain structure!

Descriptors are divided into enhanced descriptors and conventional descriptors. We only talk about conventional descriptors! Because our network routine uses only regular descriptors. Regular descriptors and enhanced descriptors have different structure member variables. The regular descriptor uses only the first four member variables of the descriptor.

Note: the descriptor mentioned here has no hardware structure and is not a register. It is a pure software concept.

So how do descriptors relate to hardware?

The essence of the descriptor is that we use the structure to implement the descriptor, and then write the first address of the descriptor into the [eth_dmatdlar] register. STM32 knows that this memory is used as the sending descriptor.

Conventional descriptors and enhanced descriptors include send descriptors and receive descriptors.

The following figure shows the general txdma descriptor:


Tdes0 is mainly used to represent the state and control information of the descriptor.

Tdes1 represents the effective length of the descriptor buffer data.

Tdes2 represents the address of the descriptor buffer. The data we want to send is placed in the memory pointed to by this address.

Tdes3 represents the address of the next descriptor.

Important information is:

Own bit in TDES 0:

0: indicates that the CPU occupies the descriptor. The CPU can extract data from DMA, but DMA cannot receive data from FIFO.

1: Indicates DMA occupancy descriptor. CPU cannot extract data from DMA, and DMA can receive data from FIFO.

DMA clears the bit to 0 ‘after transmitting a complete frame or reading all the data in the cache. The occupancy bit of the first cache descriptor of each frame must be set to ‘1’ after all the occupancy bits of the subsequent cache descriptors are set to ‘1’.

Sending process:

1. When the own bit is 0, it means that the CPU can copy the data to be sent to the descriptor. After the copy is completed, we manually set the own bit of the descriptor to 1 to tell the DMA controller that I have copied the data. You can take the data from the descriptor and send it.

2. At this time, DMA will take out the data in the descriptor and send the data. After operating the descriptor, DMA will automatically set the own bit to 0 and tell the CPU that DMA has sent the data. You can copy the data of the next frame to the descriptor.

3. At this time, own is 0. Repeat step 1

The whole sending process is coordinated in this way. In this way, data will not be preempted between DMA and CPU.

Bit 20 TCH in Des 0: second address chained

Used to indicate whether the second address in the descriptor is used to save the address of the next descriptor or the address of the second buffer.

When this position is 1, it means that the second address in the descriptor is the next descriptor address, not the second buffer address. That is, the chain structure used by the upper St.

Conventional rxdma descriptors are as follows


Bit14 of rdes1 in the conventional rxdma descriptor is used to indicate whether the second address in the descriptor is used to save the address of a descriptor or the address of the second buffer.

The performance of the descriptor in the code is shown in stm32f2x7_ In the eth. H file.

  * @brief                           DMA descriptors types

  * @brief  ETH DMA Descriptors data structure definition
typedef struct  {
  __IO uint32_t   Status;                /*!< Status */
  uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */
  uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */
  uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */
/* Enhanced ETHERNET DMA PTP Descriptors */
  uint32_t   ExtendedStatus;        /* Extended status for PTP receive descriptor */
  uint32_t   Reserved1;             /* Reserved */
  uint32_t   TimeStampLow;          /* Time Stamp Low value for transmit and receive */
  uint32_t   TimeStampHigh;         /* Time Stamp High value for transmit and receive */

03. Descriptors in the library provided by St

If DMA descriptors with link structure are used in the official Ethernet library stm32f2x7 of St, then in the Ethernet descriptor structure eth_ In dmadecttypedef, buffer1addr is the address of the buffer, and buffer2nextdescaddr is the address of the next descriptor,

See the figure below.


In stm32f2x7_ Two DMA descriptor arrays are defined in eth. C, one for DMA reception and one for DMA transmission, as follows:


The size of the receive and send description is through the macro eth_ Rxbufnb and eth_ Txbufnb. The default value is 5.

We know that the buffer1addr member of the Ethernet descriptor in the link structure is used to store the buffer address. Where is the data buffer? This data buffer is also defined as an array, as follows:


The code that links them together connects the descriptor with the buffer, that is, the following function forms the descriptor into a chain structure.

Low in ethernetif. C_ level_ In init function


The analysis is as follows


Global descriptor pointer, used to record the currently used descriptor


Describe the descriptor of the data packet (English: a structure used to store the descriptor information of the last received packet.)


structural morphology


The first represents the first descriptor of the packet, the second represents the last descriptor of the packet, and the third represents the number of packet descriptors.

The final effect is as follows:



From the STM32 network controller block diagram, you can see two 2KB FIFOs, one transmit FIFO and one receive FIFO.

send outFIFO

Two FIFO data modes are provided for frame transmission

  1. Threshold mode: when the threshold is reached, data is transmitted as soon as possible.

  2. Store and forward mode: a complete frame structure will be stored in FIFO.

The transmit FIFO of STM32 adopts store and forward mode.



Receive FIFOStore and forward mode is adoptedpattern.


Click to view the album where this article is located,Stm32f207 network development

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