Capacity expansion of SRAM


SRAM is static random access memory. The so-called “static” means that as long as the memory is powered on, the data stored in it can be kept all the time, but it will be lost after power failure. Compared with DRAM (dynamic random access memory), it doesn’t need to refresh the data periodically. It’s easy to operate and faster, but it’s more expensive, and its integration is not as high as DRAM.


In practical applications, the memory capacity is usually much larger than the capacity of the chip, so it is necessary to combine multiple chips to expand the memory capacity. Taking SRAM chip as an example, this paper systematically introduces the common methods of expanding storage capacity.

Generally, the data bus of microprocessor is 8 bits and 16 bits or 32 bits, while the address bus is 16 bits or 24 bits. WhenStatic RAMWhen the address line and data line can’t match the microcomputer, it can be solved by extending the address line and data line or extending the address line and data line at the same time.


1. Ram capacity expansion — bit expansion, data line expansion

For example, SRAM 2114 has 10 bit address and 4-bit data line, and its capacity is 210 × 4 = 1024 × 4 = 4096 word bits (4K).



Example: a ram with the capacity of 1024 × 8 (≈ 8K word bits) can be realized by using the ram 2114 with the capacity of 4K.

Solution: 1024 × 8 word bit capacity, its address is still 10 bits, so as long as the data bit expansion can be carried out, ram2114 two pieces are selected, the address line, read / write line and chip selection line of the two pieces are paralleled, the bit lines of the two pieces are respectively used as the high 4 bit data and the low 4 bit data to form an 8-bit data line. The expanded circuit is shown in the figure



2.SRAMCapacity expansion — word expansion, address expansion, data expansion.

Example: RAM 2114 is used to expand to 4096 × 8 bits (32K) ram.

Solution: 4096 needs 12 bit address, while ram2114 only has 10 bit address, so address expansion is needed. At the same time, 4 bits per word should be expanded to 8 bits per word. The bit expansion of the word is completed by the previous method, and the address expansion is completed by the decoder. The circuit expanded by 8 ram211 is shown in the figure