IIC has two kinds of lines: 1. Data line SDA; 2. Clock line SCL. The data line should cooperate with the clock on the clock line to transfer data. A pulse cycle can transmit 1 bit of data. When the clock is at high level, the data line cannot be changed. When it is at low level, it can be changed arbitrarily.
Using the data transmission mode of MSB, the high bit is transmitted first.
Note: in circuit design, clock line and data line must be connected with pull resistance respectively to provide high point flat use for circuit.
Several basic concepts of IIC are as follows
1. Start signal: when the clock line is at high level, the data line will jump along the falling edge. This signal is considered as the start signal of data transmission, indicating the start of data transmission. That is to say, when the sender begins to send data to the receiver, the sender starts to send the signal, and then the sender begins to occupy the IIC bus.
2. End signal: when the clock line is at high level, the rising edge of the data line jumps. This signal is considered as the end of data transmission signal, indicating that the transmission of data is stopped. That is to say, the sender does not want to send data to the receiver, and the signal is sent by the sender, and then the IIC bus is idle.
3. Response signal: a response signal is a signal that the receiver responds to the sender at the 9th clock pulse after each data transmission. When the signal is 0, it is a response signal, indicating that the data transmission is successful; when it is 1, it is a non response signal.
Note: the nonresponsive signal here does not mean that the receiver does not respond to the sender.
When to respond to a response and when to respond to a non response, you have to look at the specific timing diagram of the chip. Different chips have different sequence diagramsIn general, please normally receive, write normally, and respond to the response signal. If there is an exception or if you want to end this communication in advance, you usually respond to non response
Each device with IIC bus has a unique address, which is called device address. Generally, there are 7bit and 10bit, but 10bit is not commonly used. When we want to process the 10bit address, we need to use 2 bytes to process, which is more troublesome. Of course, we can also use it, but we usually use 7 bit device address + 1 bit read / write bit, which is just 1 byte, which is convenient for processing.
The arbitration mechanism of IIC is as follows:
In short, it is a selection mechanism of which host is the controller of IIC bus among multiple hosts.
1. The reason why the competition arbitration mechanism can be implemented is because of the internal leakage structure of IIC
2. When each host sends the level to the clock line, it can sense the level state of the current clock line in real time
For example, in an IIC network, there are three devices a, B and C. These three devices can be used as master-slave machines. At a certain time, all three devices send out low-level signal 0. In the transmission process, C – > 0 suddenly jumps to high-level C – > 1, At this time, C finds that there is still a low level in the line, indicating that not only C wants to communicate through the IIC bus, so the C device will be set to the receiving state (floating input); after a period of time, B – > 0 also suddenly jumps to B – > 1 high level. At this time, B finds that there is still a low level in the line, indicating that there are other hosts that want to communicate through the IIC bus, then B The device will be set to receive state (floating input); after a period of time, a – > 0 will suddenly jump to a – > 1 high level. At this time, a finds that there is a high level in the line, which indicates that no other host wants to control the IIC bus except host a. at this time, a is identified as the owner of IIC bus until a sends the end signal to make the IIC bus idle State, other hosts can own.
Note: an IIC network can have multiple hosts and slaves, but only one host can send data at a certain time, and he controls the IIC bus.
IIC communication establishment connection:
Each communication is initiated by the host. First, the host sends the start signal, and then the start signal must be followed by the device address of the target device to be broadcast, which is 7bit or 10bit + 1bitWhen other devices in the chip network receive this address and compare with their device address, if they are not the same, they will not be activated and will not participate in the subsequent communication. If a device is found and just hostsIf the broadcast address is the same, it will activate and then respond to a bit responseSignal (low level digital signal 0). The subsequent communication is set by specific chip. Finally, a host sends out a stop signal.
Send start signal — > device address (7bit) — > read-write bit (1bit) — > reply signal —– > data transmission connection ——– > reply signal —– > send end signal